MEMORY PROTECTION SYSTEM PROVIDING FIXED, CONDITIONAL AND FREE MEMORY PORTIONS CORRESPONDING TO RANGES OF MEMORY ADDRESS NUMBERS

• US 3,742,458 A
• Filed: 09/10/1971
• Issued: 06/26/1973
• Est. Priority Date: 09/30/1970
• Status: Expired due to Term

• Current Assignee: Yokogawa Electric Corporation
• Original Assignee: Shigeru Yamamoto, Tadanari Inoue, Yutaka Wakasa
• Inventors: Inoue, Tadanari, Yamamoto, Shigeru, Wakasa, Yutaka
• Primary Examiner(s): Zache, Raulfe B.
• Assistant Examiner(s): Chapnick, Melvin B.
• Application Number:
  US05/179,293
• Time in Patent Office: 655 Days
• Field of Search: 340/172.5
• US Class Current: 711/154
• CPC Class Codes: G06F 12/1441 for a range

Abstract

A method and apparatus for flexible protection against overwriting and destruction of the contents of selected portions of a computer memory device formed of a multiplicity of memory units. Each memory unit is assigned a unique memory address number which serves to identify the memory unit in instructions to write data into the memory. The address numbers are segregated into ranges of numbers defining separate memory portions to be protected, with the numbers at the limits or boundaries of the ranges being entered in registers which can be reset to flexibly determine the protected ranges. The memory device is separated in this fashion into three different portions: one permitting free writing access to the memory units, one withholding all writing access to the memory units, and one being conditioned to grant or withhold writing access according to the setting of a device such as flip-flop which can be arranged for manual or programable control. Whenever an instruction to alter a memory unit arises, the associated address number is entered in a register and compared by means of digital comparators with the range boundary numbers in their registers. Gate means grant or withhold access to the memory unit in accordance with the comparison, thereby controlling the insertion of data into each memory unit and providing protection for selected portions of the memory device.

Claims

1. A method for protecting the contents of selected portions of a memory device formed of a multiplicity of memory units, said method comprising:

assigning a unique address number to each memory unit, designating three contiguous ranges of address numbers to correspond to memory portions to be protected, said ranges being designated by selecting address numbers at the limits of said ranges, said ranges of address numbers including a first range to which access is always withheld, a second range to which access is conditioned upon the setting of a control device, and a third range to which access is always granted, setting said control device to condition said second range to grant or withhold access to the corresponding memory portion;

associating every instruction for altering a memory unit with the address number of that unit, as each instruction to alter memory is presented, comparing the address number associated with the memory unit with said designated ranges to determine whether that address number is within a protected range and therefore the corresponding memory unit to be protected, and withholding or granting access to said memory units in response to and in accordance with said comparison, thereby protecting the contents of portions of the memory device.

2. A method for protecting memory con-tents as claimed in claim 1 wherein said three ranges are designated by selecting two address numbers to act as limits between said ranges, storing said limit numbers in two set registers, and wherein said address numbers are entered in a register and compared in digital comparing means with the limit numbers in said registers, and gating the outputs of the digital comparing means to generate signals to correspond to withholding or granting access to the memory units.

3. An apparatus for restricting access to preselected portions of a memory device formed of a multiplicity of memory units, wherein each memory unit is assigned a unique address number to be associated with memory instructions relating to that memory unit, said apparatus comprising:

input means for receiving an address number associated with a memory instruction, means for designating three contiguous ranges of address numbers to correspond to the portions of the memory device to be protected, said ranges of address numbers including a first range to which access is always withheld, a second range to which access is conditioned upon the setting of a control device, and a third range to which access is always granted, said range designating means compRise means for registering two address numbers to act as limits between said ranges, and means for coupling the address numbers with said two registered limit numbers to determine whether access is to be given to the corresponding memory unit, and means for withholding or granting access to said memory unit in response to said comparing means.

4. An apparatus for protecting portions of a memory device as claimed in claim 3 wherein said range designating means is settable to provide preselected range boundaries, whereby said ranges can provide desired limits of memory protection.