DATA SYNCHRONIZING UNIT FOR DATA TRANSMISSION SYSTEM

• US 3,742,462 A
• Filed: 02/17/1972
• Issued: 06/26/1973
• Est. Priority Date: 03/02/1970
• Status: Expired due to Term

• Current Assignee: Carl M. Solar, Donald E. Haselwood
• Original Assignee: Carl M. Solar, Donald E. Haselwood
• Inventors: Haselwood, Donald E., Solar, Carl M.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US05/227,143
• Time in Patent Office: 495 Days
• Field of Search: 340/172.5
• US Class Current: 375/354
• CPC Class Codes: H04H 2201/37 via a different channel
• CPC Class Codes: H04H 60/32 Arrangements for monitoring conditions of receiving stations, e.g. malfunction or breakdown of receiving stations
• CPC Class Codes: H04H 60/43 for identifying broadcast channels
• CPC Class Codes: H04H 60/94 Telephonic networks for accessing the Internet H04H60/84

Abstract

A data synchronizing unit analyzes an incoming data signal and generates a strobe signal at times when data bits may be extracted from the incoming data signal with the least chance of error. The synchronizing unit makes it possible to transmit a continuous stream of data bits from one location to another without using stop and start codes and without transmitting a stream of timing or synchronization signals along with the data bits. A variable-mod counter generates a square wave signal the leading edge of which is the desired strobe signal. A constant frequency source drives the counter at a frequency which precisely equates the normal period of the counter-generated square wave signal with the time allotted to the transmission of one data bit. A digital phase detector keeps the trailing edge of the square wave signal phase-locked with level transitions of the incoming signal by slightly increasing or decreasing the counter mod number whenever a phase error appears. A starting circuit initializes the variable-mod counter phase-locked with the first level transition of the incoming signal and thus avoids any delay before phase-lock is achieved.

Claims

1. A data synchronizing unit for extracting data bits from an incoming signal comprising:

a counter having an input and an output;

mod increasing circuit means connected to said counter for increasing the mod of the counter;

mod decreasing circuit means connected to said counter for decreasing the mod of the counter;

a source of fixed frequency pulses connected to the input of the counter and having a frequency chosen so that the counter output normally fluctuates at the bit transmission frequency of the incoming signal;

means for generating a level transition signal each time the incoming changes its level and comprising two flip-flops both connected to the incoming signal, one of which is arranged to toggle upon positive fluctuations in the incoming signal and the other of which is arranged to toggle upon negative fluctuations in the incoming signal, and the output of said two flip-flops being ORed together to form a single level transition signal; and

phase comparison means for comparing the phase of said level transition signal to the phase of the counter output and for energizing the mod increasing circuit means and the mod decreasing circuit means as needed to keep the counter output in phase with the level transition signal.

2. A data synchronizing unit for extracting data bits from an incoming signal comprising:

a counter having an input and an output, and including means for generating approximately a square wave output signal;

mod increasing circuit means connected to said counter for increasing the mod of the counter;

mod decreasing circuit means connected to said counter for decreasing the mod of the counter;

a source of fixed frequency pulses connected to the input of the counter and having a frequency chosen so that the counter output normally fluctuates at the bit transmission frequency of the incoming signal;

means for generating a level transition signal each time the incoming signal changes its level;

strobing means for causing the incoming signal to be strobed for data bits in synchronism with one edge of said counter square wave output signal; and

phase comparison means for comparing the time of occurance of each of said level transition signals with the time of occurance of the other edge of said counter square wave output signal and for energizing the mod increasing circuit means and the mod decreasing circuit means as needed so as to minimize the time lag between the occurance of the level transition signal and said other edge of said square wave signal, thereby keeping said counter output in approximate phase with the level transition signal.

3. A data synchronizing unit for extracting data bits from an incoming signal comprising:

a counter having an input and an output;

mod increasing circuit means connected to said coUnter for increasing the mod of said counter;

mod decreasing circuit means connected to said counter for decreasing the mod of said counter;

a source of fixed frequency pulses connected to the input of said counter and having a frequency chosen so that the counter output normally fluctuates at the bit transmission frequency of the incoming signal;

means for generating a level transition signal each time the incoming signal changes its level; and

phase comparison means for comparing the phase of said level transition signal to the phase of the counter output and for energizing the mod increasing circuit means and the mod decreasing circuit means as needed to keep the counter output in phase with the level transition signal, said phase comparison means comprising a first gate receiving as inputs the counter output and a level transition signal and having an output connected to one of said mod increasing or decreasing circuit means, and a second gate receiving as inputs the inverted counter output and the level transition signal, and having an output connected to the other of said mod increasing or decreasing circuit means.

4. A data synchronizing unit in accordance with claim 3 wherein the mod increasing and decreasing circuit means each comprise two flip-flops, wherein the first flip-flop is connected to and set by the output signal of one of the phase comparison gates, wherein the second flip-flop is connected to and enabled by an output of the first flip-flop, wherein the second flip-flop is connected to and is set by the counter output signal when enabled by said first flip-flop and is connected to and cleared by a subsequent high frequency pulse, and wherein the output of said second flip- is fed into and is used to alter the mod of the counter.

5. A data synchronizing unit for extracting data bits from an incoming signal comprising:

a counter having an input and an output and including an inhibit input to which a signal may be applied so as to inhibit the counter from advancing;

mod increasing circuit means connected to said counter for increasing the mod of the counter;

mod decreasing circuit means connected to said counter for decreasing the mod of the counter;

a source of fixed frequency pulses connected to the input of the counter and having a frequency chosen so that the counter output normally fluctuates at the bit transmission frequency of the incoming signal;

means for generating a level transition signal each time the incoming signal changes its level;

phase comparison means for comparing the phase of said level transition signal to the phase of the counter output and for energizing the mod increasing circuit means and the mod decreasing circuit means as needed to keep the counter output in phase with the level trasnition signal;

means for generating a carrier present signal whenever said incoming signal is present; and

starting circuit means for supplying an inhibit signal to said counter inhibit input when said counter reaches a predetermined count and when said carrier present signal is absent, said starting circuit means including means for terminating said inhibit signal upon the occurrence of a level transition signal following the recommencement of said carrier present signal;

whereby the counter may be started in approximate phase synchronization with the onset of the incoming signal.

6. A data synchronizing unit in accordance with claim 5 wherein the starting circuit means comprises a flip-flop having an output connected to the counter inhibit input, having a toggle input connected to the counter output, having an additional direct clear input connected to the carrier present signal and to the level transition signal by an AND gate, and including J and K inputs connected respectively to the carrier present signal and to a source of potential in such a manner that the toggle input is inhibited whenever the carrier present signal is present but so that the toggle inpUt allows the flip-flop to be toggled so as to generate the inhibit signal whenever the carrier present signal is absent.

7. A data transmission system for transmitting binary data, said system comprising:

Data transmission means having a binary data input at one location and having a binary data output at another location and comprising an audio communications channel, first and second sources of audio tone, gating means responsive to the data presented at said binary data input for connecting the one or the other of said audio tones to one end of said audio communications channel, and frequency modulation receiver means connecting the other end of said communications chennel to said binary data output for converting tones re-ceived from said channel into a binary signal whose state depends upon the frequency of the tone;

data presentation means connected to said binary data input for serially presenting data to the input at a first bit presentation rate;

level transition detection means connected to said binary data output for generating a level transition signal in response to said binary data output changing its state;

a variable mod counter having an input and generating a strobe output signal;

an oscillator connected to said variable mod counter input and operating at a second rate chosen to cause said strobe output signal to fluctuate at said first bit presentation rate; and

phase detection means for comparing the phase of said strobe output signal to the phase of said level transition signal and for varying the modulus of the counter as needed to keep these signals phased properly;

whereby the strobe output signal indicates the proper times to sample data bits presented at binary data outputs of said data transmission means.