NONINDUCTIVE EQUALIZING NETWORK

• US 3,743,957 A
• Filed: 12/03/1971
• Issued: 07/03/1973
• Est. Priority Date: 12/04/1970
• Status: Expired due to Term

• Current Assignee: Karl Heinz Feistel
• Original Assignee: Karl Heinz Feistel
• Inventors: Feistel, Karl Heinz
• Primary Examiner(s): Lake, Roy
• Assistant Examiner(s): Mullins, James B.
• Application Number:
  US05/204,583
• Time in Patent Office: 578 Days
• Field of Search: 330/107,109,151,85,21 WIN/ETAL.,"A
• US Class Current: 330/85
• CPC Class Codes: H03H 11/1252 Two integrator-loop-filters
• CPC Class Codes: H04B 3/14 characterised by the equalising network used
• CPC Class Codes: H04B 3/141 using multiequalisers, e.g. bump, cosine, Bode

Abstract

An equalizing network for correcting phase and amplitude distortions comprises three cascaded operational-amplifier stages, all with grounded noninverting inputs, the first two of them having capacitive feedback to operate as inverting integrators while the third one has a resistive feed-back to function as a summing inverter. The first stage receives on its inverting input, by way of identical resistors, the input voltage and the output voltage of the network and feeds the inverting input of the second stage through an adjustable resistor serving for selection of the frequency of maximum or minimum attenuation. The last-mentioned input also receives the input voltage and the inverted output voltage through respective branches of a potentiometer, serving for adjustment of the attenuation, whose slider is in series with a further adjustable resistor controlling the phase delay. The connection between the potentiometer extremities and the network terminals may include a reversing switch to change the sign of the attenuation.

Claims

1. An equalizing network comprising:

an input terminal, an output terminal and a common terminal;

a first, a second and a third operational amplifier connected in cascade between said input and output terminals, said first and second amplifiers being connected as integrators, said third amplifier being connected as a summer, each of said amplifiers having an output circuit, a live input lead and another input lead connected to said common terminal;

a first resistor inserted between said input terminal and the live input lead of said first amplifier;

a second resistor inserted between said output terminal and the live input lead of said first amplifier;

a third resistor inserted between the output circuit of said second amplifier and the live input lead of said third amplifier;

a fourth resistor inserted between said input terminal and the live input lead of said third amplifier, the output circuit of the latter being connected to said output terminal;

a fifth resistor inserted between the output circuit of said first amplifier and the live input lead of said second amplifier;

a noninverting first resistance path extending from said input terminal to the live input lead of said second amplifier;

a polarity-inverting second resistance path extending from said output terminal to the live input lead of said second amplifier, said resistance paths being provided with control means for jointly varying the magnitudes of their respective resistances while holding the sum of said magnitudes constant; and

an adjustable sixth resistor common to both said resistance paths.

2. A network as defined in claim 1 wherein said amplifiers all have inverting inputs connected to said live input leads thereof.

3. A network as defined in claim 2 wherein said first and second resistors are of the same magnitude.

4. A network as defined in claim 3 wherein said thiRd amplifier is provided with a feedback resistor of the same magnitude as said fourth resistor.

5. A network as defined in claim 2 wherein said second resistance path includes an inverting fourth operational amplifier in series with said sixth resistor and provided with an inverting input connected to said output terminal.

6. A network as defined in claim 5 wherein said control means comprises a potentiometer with first and second branches respectively included in said first and second resistance paths.

7. A network as defined in claim 6 wherein said fourth amplifier is inserted between said output terminal and the second branch of said potentiometer.

8. A network as defined in claim 7 wherein said potentiometer has a slider connected through said sixth resistor to the live input lead of said second amplifier.

9. A network as defined in claim 6 wherein said potentiometer has a slider connected to the inverting input of said fourth amplifier, said second branch being connected to said output terminal, further comprising an inverting fifth operational amplifier inserted between said input terminal and said first branch.

10. A network as defined in claim 6, further comprising a reversing switch connected to said potentiometer for interchanging the connection of said branches in said first and second resistance paths.