COHERENT DIGITAL MULTIFUNCTION PROCESSOR

• US 3,745,571 A
• Filed: 02/18/1972
• Issued: 07/10/1973
• Est. Priority Date: 02/18/1972
• Status: Expired due to Term

• Current Assignee: Adolph M. Chwastyk, Alan M. Diamant
• Original Assignee: Adolph M. Chwastyk, Alan M. Diamant
• Inventors: Chwastyk, Adolph M., Diamant, Alan M.
• Primary Examiner(s): Hubler, Malcolm F.
• Application Number:
  US05/227,586
• Time in Patent Office: 508 Days
• Field of Search: 343/17.2PC,7.7,5DP,1CL
• US Class Current: 342/194
• CPC Class Codes: G01S 13/524 based upon the phase or frequency shift resulting from movement of objects, with reference to the transmitted signals, e.g. coherent MTi
• CPC Class Codes: G01S 13/53 performing filtering on a single spectral line and associated with one or more range gates with a phase detector or a frequency mixer to extract the Doppler information, e.g. pulse Doppler radar G01S13/5244 takes precedence
• CPC Class Codes: G01S 13/64 Velocity measuring systems using range gates

Abstract

A coherent digital multifunction processor that is capable of multiple-mode processing and can also perform rapid inter-mode switching. Additionally, while processing data in a given mode, the subject processor is capable of self-synchronization, thereby obviating the requirement for external synchronous devices. The instant processor has a central control which may suitably utilize a general purpose computer in one embodiment. The primary modes of operation of the subject processor are: a pulse doppler acquisition and/or tracking mode, a moving target indicator mode, and an incoherence mode.

Claims

1. In a coherent, multifunction processor for accepting encoded waveforms and for performing coherent processing thereupon, the combination comprising;

variable attenuation means receiving and attenuating said encoded waveforms whenever a predetermined signal strength is received therein;

mixer means responsive to said attenuated encoded signal for dividing said attenuated encoded signal into coded and uncoded in-phase and quadrature-phase video components;

means operably connected to said mixer means for match-filtering said uncoded video components;

means operably connected to said mixer means for compressing said coded video components;

converting means receiving said filtered uncoded video components and said compressed coded video components for converting all of said components into a predetermined data format;

signal synchronizing means responsive to the output of said converting means for providing signal-type identification of said converted signal;

signal processing means receiving the output of said signal synchronizing means for extracting the information content from said synchronized signal; and

mode control means Operably connected to said signal synchronizing means and to said signal processing means for controlling the operation of said signal synchronizing processing means, wherein the manner of said control is dependent upon the characteristics of said encoded waveforms.

2. The processor as claimed in claim 1 wherein signal-type identification is either in a moving target indicator mode or in a pulse doppler mode and further wherein said manner of control of said mode control means is also determined by said signal-type identification.

3. The processor as claimed in claim 2 wherein said variable attenuation means is a digital sensitivity time control/automatic gain control circuit having a plurality of attenuation slopes.

4. The processor as claimed in claim 3 wherein said converting means is an analog-to-digital converter.

5. The processor as claimed in claim 4 wherein said sensitivity time control/automatic gain control circuit is regulated by said mode control means.

6. The processor as claimed in claim 5 wherein said match-filter means comprises delay line circuit means receiving the output of said mixing means for delaying in time said mixed signal;

and integrating circuit means responsive to the output of said delay line circuit means for integrating said delayed output signal.

7. The processor as claimed in claim 6 wherein said compressing means comprises video delay line means operably connected to said mixing means, for delaying in time said coded video components, said video delay line means producing therefrom a coded pulse output;

and means receiving said coded pulse output of said video delay line means for compressing in time said coded pulse output.

8. The processor as claimed in claim 7 wherein said pulse compression means is a resistive decoding circuit.

9. The processor as claimed in claim 8 wherein said signal processing means is an expandable wired-program circuit means for performing coherent multiply-add cycles in the computation of discrete Fourier transforms of the echo signals in the pulse doppler mode and to null the return of a specific doppler response in the moving target indicator.

10. The processor as claimed in claim 9 wherein said signal processing means comprises:

arithmetic means receiving the output of said analog-to-digital converting means for sampling said incoming video data at predetermined intervals, for converting said sampled data into the proper format and for weighing said converted data by vector rotation;

sine/cosine generating means operably connected to said arithmetic means for providing direction input to said arithmetic means during said pulse doppler mode; and

program control register means responsive to said sine/cosine generating means for directing said sine/cosine generating means and for supplying command information to the signal processing unit.

11. The processor as claimed in claim 10 wherein said signal processing means further comprises central computer control means for storing the processed video at the end of a dwell if said mode control means is in a pulse doppler mode or for adding the processed video to a coherent running sum if said mode control means is in said moving target indicator mode.

12. The processor as claimed in claim 11 wherein said arithmetic means performs summation, square root and peak select computations when said processed video is to be added to a coherent running sum.