PROGRAMMABLE ELECTRIC LOCKING SYSTEM
First Claim
1. A programmable electric locking system including an electrically operated door latch, comprising:
- a switch;
a timing light visible to an operator of said switch;
timing means for generating timing signals;
a memory register connected to receive said timing signals for storing a binary one or a binary zero during each succeeding timing signal;
means connecting said switch to said memory register for entering binary ones or binary zeros during each timing signal;
means connecting said timing signal to said timing light for energizing said light to indicate to an operator when said switch may be operated to enter binary ones or binary zeros in said memory register;
a decoding circuit connected to said memory register and responsive to a predetermined combination of binary ones or binary zeros stored in said memory register for generating an unlocking signal for energizing said electrically operated door latch.
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Abstract
An electric locking system including an electrically operated door latch wherein the latch is energized by a signal derived from logic circuitry. The system is provided with a switch and a timing light; the initial closure of the switch activates the timing light for successive periods of time. During each of the successive periods of time, a memory register is enabled and activation of the switch during one of these periods of time will result in the storage of a binary one in the memory register. When the timing light has been energized and the memory register enabled a predetermined number of times, a logic gate is enabled and the contents of the memory register are applied to the gate; if the contents of the memory register coincide with a preselected binary code, an unlocked signal causes the energization of the electrical latch mechanism to thereby unlock the door.
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Citations
7 Claims
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1. A programmable electric locking system including an electrically operated door latch, comprising:
- a switch;
a timing light visible to an operator of said switch;
timing means for generating timing signals;
a memory register connected to receive said timing signals for storing a binary one or a binary zero during each succeeding timing signal;
means connecting said switch to said memory register for entering binary ones or binary zeros during each timing signal;
means connecting said timing signal to said timing light for energizing said light to indicate to an operator when said switch may be operated to enter binary ones or binary zeros in said memory register;
a decoding circuit connected to said memory register and responsive to a predetermined combination of binary ones or binary zeros stored in said memory register for generating an unlocking signal for energizing said electrically operated door latch.
- a switch;
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2. A programmable electric locking system including an electrically operated door latch comprising:
- a switch;
a timing light visible to an operator of said switch;
timing means for generating timing signals;
a cycle counter connected to receive said timing signals and to generate a cycle signal in response to each successive predetermined number of timing signals;
a memory register connected to receive said cycle signals for storing a binary one or a binary zero during each succeeding cycle signal;
means connecting said switch to said memory register for entering binary ones or binary zeros during each cycle signal;
means connecting said cycle signal to said timing light for energizing said light to indicate to an operator when said switch may be operated to enter binary ones or binary zeros in said memory register;
a decoding circuit connected to said memory register and responsive to a predetermined combination of binary ones and binAry zeros stored in said memory register for generating an unlocking signal for energizing said electrically operated door latch.
- a switch;
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3. The combination set forth in claim 2, wherein said memory register includes a plurality of memory cells, each for storing, when enabled, a binary one or a binary zero and wherein each succeeding cycle signal received by said memory register enables said memory cells.
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4. The combination set forth in claim 3, wherein said memory register is a serial in, parallel out, binary register for serially receiving binary information for storage therein and for providing said stored binary information in parallel.
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5. The combination set forth in claim 3, wherein said timing light includes an indicator for numerically indicating the code digit position then being encoded by said switch.
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6. A programmable electric locking system including an electrically operated door latch, comprising:
- a switch;
a timing light visible to an operator of said switch;
a free running oscillator having an adjustable frequency of oscillation for generating timing signals;
a cycle counter connected to receive said timing signals and to generate a cycle signal in response to each successive predetermined number of timing signals, said cycle counter connected to said switch and responsive to an initial closure of said switch to initiate counting of said timing signals and generation of said cycle signals by said cycle counter;
a memory register connected to receive said cycle signals and having a plurality of memory cells, each for storing, when enabled, a binary one or a binary zero, each succeeding cycle signal received by said memory register enabling said memory cells;
means connecting said switch to said memory register for entering binary ones or binary zeros in said memory cells when said cells are enabled;
means connecting said cycle counter to said timing light for energizing said light when said counter generates cycle signals to indicate to an operator when said memory cells are being enabled;
a decoding circuit connected to said memory register and responsive to a predetermined combination of binary ones and binary zeros stored in said memory cells for generating an unlocking signal.
- a switch;
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7. The combination set forth in claim 6, wherein said decoding circuit includes an inverter connected to each of said memory cells for inverting the binary contents thereof and wherein said decoding circuit includes a plurality of switches, each corresponding to a different one of said memory cells, each of said switches positionable to connect the contents of the corresponding memory cell or the inverse of the contents of the corresponding memory cell to a logic gate.
Specification