CHARGE PARCELLING INTEGRATOR

• US 3,754,234 A
• Filed: 10/18/1971
• Issued: 08/21/1973
• Est. Priority Date: 10/18/1971
• Status: Expired due to Term

• Current Assignee: Bernard T. Murphy, Rein R. Laane
• Original Assignee: Bernard T. Murphy, Rein R. Laane
• Inventors: Laane, Rein R., Murphy, Bernard T.
• Primary Examiner(s): Sloyan, Thomas J.
• Application Number:
  US05/190,400
• Time in Patent Office: 673 Days
• Field of Search: 340/347 307/229,246,234,270 328/67,78,127 325/38B
• US Class Current: 341/150
• CPC Class Codes: H03M 3/02 Delta modulation, i.e. one-bit differential modulation H03M3/30 takes precedence

Abstract

An integrator network for use in signal conversion systems uses charge parcelling techniques to transmit pulses to the integrating capacitor as quanta of charge. A compensation network corrects imbalances between the input pulses.

Claims

1. A delta modulation decoder for translating digital signal pulses into an analog voltage comprising:

a source of timing pulses occurring at the rate of said digital signal pulses;

a first capacitor, the voltage on said first capacitor representing said analog voltage;

means, responsive to said timing pulses, for increasing the charge stored on said first capacitor, including a second capacitor and a first switching means for coupling said first and second capacitors;

means, responsive to said digital signal pulses, for decreasing the charge stored on said first capacitor, including a third capacitor and a second switching means for coupling said first and third capacitors; and

means responsive to the voltage across said first capacitor for regulating a charging of said second capacitor after said second capacitor has been decoupled from said first capacitor;

whereby the coupling of respective capacitors by associated switching means enables the transfer of an amount of charge proportional to the capacitances of said respective capacitors.

2. A delta modulation decoder as described in claim 1 wherein said means for regulating a charging includes:

a resistor;

means responsive to a voltage change on said first capacitor for establishing a current flow in said resistor; and

means responsive to the current flow in said resistor for regulating the recharging of said second capacitor after said second capacitor has been decoupled from said first capacitor.

3. A delta modulation decoder as described in claim 1 wherein said means for regulating a charging includes active circuit means for varying the charging of said second capacitor in a manner which is a linear function of voltage changes on said first capacitor, whereby the voltage on said first capacitor is prevented from drifting to voltage extremes otherwise permitted in said decoder.

4. An integration circuit for producing an analog signal in response to clock pulses and a binary signal encoded in delta modulation form with a bit rate equal to the rate of said clock pulses, said integrator circuit comprising:

an integrating capacitor;

means, responsive to each of said clock pulses, for charging said capacitor; and

means responsive to one logical state in said binary signal, for discharging said capacitor by two quanta of charge;

characterized in that said means for charging includes a second capacitor having one plate coupled to receive said clock pulses, a unilateral switching means for coupling a second plate of said second capacitor to said integrating capacitor in response to a voltage change produced on said second plate by one of said clock pulses; and

mans responsive to said clock pulses and to a stored voltage across said integrating capacitor for charging the second plate of said second capacitor to a potential which is a function of the stored voltage across said integrating capacitor prior to a next coupling by said unilateral switching means;

whereby the amount of charge transfered to said integrating capacitor is varied as a function of the voltage of said integrating capacitor.

5. An integrator as described in claim 4 wherein said means for charging the second plate of said second capacitor includes a resistor first circuit means for producing a current flow in said resistor proportional to the voltage change on said integrating capacitor;

and second circuit means responsive to said current flow for controlling the voltage accumulated on said second plate of said second capacitor subsequent to each decoupling of said integrating capacitor and said second capacitor.

6. In a system having a source of digital pulses and a source of timing pulses, an integrator network comprising:

an integrating capacitor having a first terminal maintained at a datum voltage;

first and second input capacitors responsive respectively to timing pulses and to digital signal pulses;

a first diode having its anode connected to said first input capacitor and its cathode connected to a second terminal of said integrating capacitor, each one of said timing pulses causing a voltage differential across said first diode sufficient to cause conduction and to enable the transfer of a predetermined quantum of charge from said first input capacitor to said integrating capacitor;

sources of positive and negative potential;

a first transistor having its base connected to said source of negative potential, its collector connected to the second terminal of said integrating capacitor, and its emitter connected to said second input capacitor, each one of said digital signal pulses causing a voltage differential between the base and emitter of said first transistor sufficient to cause conduction and to enable the transfer of two of said predetermined quantum of charge from said integrating capacitor to said second input capacitor;

a second diode having its anode connected to said second input capacitor and its cathode connected to said source of negative potential;

a second transistor having its emitter connected to said first input capacitor and its collector connected to said source of positive potential; and

balanced circuit means for producing a voltage proportional to the voltage on said integrating capacitor at the base of said second transistor such that the recharging of said first input capacitor is correspondingly regulated;

whereby the voltage on said integrating capacitor represents an analog voltage which increases upon receipt of clock pulses and decreases upon receipt of digital signal pulses.