RESPONSIVE POWER-FAIL DETECTION SYSTEM

• US 3,757,302 A
• Filed: 11/16/1971
• Issued: 09/04/1973
• Est. Priority Date: 11/16/1971
• Status: Expired due to Term

• Current Assignee: Gary L. Pollitt
• Original Assignee: Gary L. Pollitt
• Inventors: Pollitt, Gary L.
• Primary Examiner(s): Yusko, Donald J.
• Application Number:
  US05/199,188
• Time in Patent Office: 658 Days
• Field of Search: 340/147R,147P,248B,419 317/22 322/11 307/87
• US Class Current: 714/22
• CPC Class Codes: G01R 19/16547 voltage or current in AC supplies switching for protection H02H; circuits for emergency power supply H02J9/00
• CPC Class Codes: G01R 31/50 Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections testing of sparking plugs H01T13/58
• CPC Class Codes: G01R 31/52 Testing for short-circuits, leakage current or ground faults
• CPC Class Codes: G01R 31/54 Testing for continuity
• CPC Class Codes: G05F 1/577 for plural loads
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: H02H 3/066 Reconnection being a consequence of eliminating the fault which caused disconnection

Abstract

An electronic system which automatically monitors the amplitude of a single phase AC or DC power source and provides electrical signals whenever a power-fail condition is detected and, afterwards, whenever a power-recovery condition is detected. The electrical signals provided by the present invention are typically routed to an operating system which derives its primary power from the monitored power source, such as, for example, a digital computer. The signals enable the operating system to go through an orderly termination of its operation under a powerfail condition. In the case of a computer, a termination sequence may be initiated and data properly stored before power is shutdown and all operations cease. When a power-recovery condition is detected, the present invention provides electrical signals which enable the operating system to restart in a programmed manner. The present invention is comprised of a novel combination of electronic switches, logic circuits, latches, timing and delay circuits and a voltage comparator circuit.

Claims

1. A system for detecting the presence and absence of power-fail conditions in a primary power source and issuing responsive signals to an operating system which derives power from said primary power source, said signals enabling said operating system to shut-down its operation in a predetermined manner when a power-fail condition is detected, and to start-up its operation in a predetermined manner when a power-recovery condition is detected after a shut-down comprising:

a. means for deriving a reference voltage whose amplitude represents a minimum acceptable amplitude of said primary power source voltage;

b. means for comparison of said primary power source voltage with said reference voltage, said primary power source and said means for deriving a reference voltage being electrically coupled to said means for comparison, said means for comparison being adapted to provide at its output a power-fail signal when said primary power source voltage is less than said reference voltage, and a power-recovery signal when said primary power source voltage is equal to or greater than said reference voltage;

c. a first one-shot pulse generator electrically coupled to said output of said means for comparison, said first one-shot pulse generator being adapted to provide at its output a single pulse of duration Tau 1 in response to each appearance of said power-fail signal;

d. a second one-shot pulse generator electrically coupled to said output of said first one-shot pulse generator, said second one-shot pulse generator being adapted to provide at its output a single pulse of duration Tau 2 in response to the trailing edge of each pulse provided by said first one-shot pulse generator;

e. a first gate having first and second input legs, said first and second input legs thereof being electrically coupled to (i) said output of said means for comparison, and (ii) said output of said second one-shot pulse generator, respectively, said first gate being adapted to provide at its output said powerfail signal if and only if said power-fail signal is present at said first input leg thereof contemporaneously with the presence of a pulse generated by said second one-shot generator at said second input leg thereof;

f. a first latch electrically coupled to said output of said first gate, said first latch having an output which is in either of first or second binary states, said first and second binary states representing said power-fail and power-recovery signals respectively, said output of said first latch assuming said first binary state when said power-fail signal appears at said output of said first gate;

g. first means for electrically coupling said output of said first latch to said operating system;

h. first means for delay electrically coupled to said output of said first latch, said first means for delay providing at its output said power-fail signal after a delay of duration Tau 3;

i. a second gate having first and second input legs, said first input leg thereof being electrically coupled to said output of said first means for delay, said second gate being adapted to provide at its output said power-fail signal when said power-fail signal appears at said first input leg thereof;

j. a second latch electrically coupled to said output of said second gate, said second latch having an output which is in either of first or second binary states, said first and second binary states representing said power-fail and power-recovery signal respectively, said output of said second latch assuming said first binary state when said power-fail signal appears at said output of said second gate;

k. second means for delay electrically coupled to said output of said second latch, said second means for delay being adapted to provide at its output (i) said power-fail signal with substantially no delay when said output of said second latch assumes said first binary state, and (ii) said power-recovery signal after a delay of duration Tau 4 following the assumption by said output of said second latch of said second binary state;

l. second means for electrically coupling said output of said second means for delay to a power dump circuit adapted to (i) shut-down at least one power supply of said operating system when said power-fail signal appears at said output of said second means for delay, and (ii) to activate said power supply when said power-recovery signal appears at said output of said second means for delay;

m. third means for delay electrically coupled to said power supply of said operating system, said third means for delay being adapted to provide at its output (i) a power-off signal with substantially no delay following the shut-down of said power supply, and (ii) a power-on signal after a delay of duration Tau 5 following the activation of said power supply;

n. third means for electrically coupling said output of said third means for delay to said operating system;

o. fourth means for delay electrically coupled to said output of said third means for delay, said fourth means for delay being adapted to provide at its output (i) said power-off signal with substantially no delay, and (ii) said power-on signal after a delay of duration Tau 6 following the appearance of said power-on signal at said output of said third means for delay;

p. fourth means for electrically coupling said output of said fourth means for delay to said operating system;

q. a start-up oscillator electrically coupled to said output of said third means for delay, said start-up oscillator being adapted to provide at its output a train of start-up pulses when said power-off signal appears at said output of said third means for delay;

r. a third gate having first and second input legs, said first and second input legs thereof being electrically coupled to (i) said output of said means for comparison, and (ii) said output of said start-up oscillator, respectively, said third gate being adapted to provide at its output said train of start-up pulses if and only if said power-recovery signal is present at said first input leg thereof contemporaneously with the presence of said pulses at said second input leg thereof;

said output of said third gate being electrically coupled to said first and second latches, said outputs of said first and second latches assuming said second binary state when said start-up pulse appears at said output of said third gate;

s. a fourth gate having first and second input legs, said first and second input legs thereof being electrically coupled to (i) said output of said means for comparison, and (ii) said output of said third means for delay, respectively, said fourth gate being adapted to provide at its output said power-fail signal if and only if said power-fail signal is present at said first input leg thereof contemporaneously with the presence of said power-off signal at said second input leg thereof;

said output of said fourth gate being electrically coupled to said second input leg of said second gate, said second gate being adapted to provide at its output said power-fail signal when said power-fail signal appears at said second input leg thereof; and

t. a DC power source, said DC power source deriving its power from said primary power source.

2. The responsive power-fail detection system of claim 1 having in addition thereto:

i. means for rectifying;

ii. means for filtering; and

iii. means for clipping said primary power source voltage when said primary power source is AC.

3. The responsive power-fail detection system of claim 1 having in addition thereto means for holding any point to which it is electrically coupled to a voltage which simulates the presence of a power-fail signal when said DC power source drops below a predetermined level, said means For holding being electrically coupled to (i) said output of said first gate, and (ii) to second said means for electrically coupling, thereby ensuring (i) that said output of said first latch remains in said first binary state, and (ii) that said power-fail signal is coupled to said power dump circuit during period when said DC power source drops below said predetermined level.

4. The responsive power-fail detection system of claim 1 having in addition thereto a magnetically biased relay having a coil which is electrically coupled to said output of said first latch and at least two contacts which are arranged and configured to provide to said operating system said power-fail signal when said coil is unenergized and said power-recovery signal when said coil is energized, said coil being unenergized when said output of said first latch is in said first binary state and energized when said output of said first latch is in said second binary state.

5. The responsive power-fail detection system of claim 1 wherein each of said first, second, third and fourth gates is a NAND gate comprised of integrated diode-transistor logic circuits and wherein each of said first, second, third and fourth means for electrically coupling comprises at least one inverter, said inverter being comprised of integrated diode-transistor logic circuits.

6. The responsive power-fail detection system of claim 1 wherein all of said NAND gates, inverters and means for delay are binary devices having first and second states, and said power-fail and power-recovery signals are represented by said first and second states respectively.

7. The responsive power-fail detection system of claim 1 wherein said means for comparison is a means which continually compares said primary power source voltage with said reference voltage.

8. A system for detecting the presence and absence of power-fail conditions in a primary power source and issuing responsive signals to an operating system which derives power from said primary power source, said signals enabling said operating system to shut-down its operation in a predetermined manner when a power-fail condition is detected, and to start-up its operation in a predetermined manner when a power-recovery condition is detected after a shut-down comprising:

a. means for deriving a reference voltage whose amplitude represents a minimum acceptable amplitude of said primary power source voltage;

b. means for comparison of said primary power source voltage with said reference voltage, said primary power source and said means for deriving a reference voltage being electrically coupled to said means for comparison, said means for comparison being adapted to provide at its output a power-fail signal when said primary power source voltage is less than said reference voltage, and a power-recovery signal when said primary power source voltage is equal to or greater than said reference voltage;

c. means for discriminating said power-fail signals of sufficient duration to warrant a shut-down of said operating systems from those which do not, said means for discriminating being electrically coupled to said means for comparison and providing at its output said power-fail signal when said shut-down is warranted;

d. first means for information storage having a first input leg electrically coupled to said output of said means for discriminating and an output electrically coupled to said operating system, said means for information storage storing and providing at its output said power-fail signal when said power-fail signal appears at said input thereof;

e. first means for delay electrically coupled to said first means for information storage, said first means for delay providing at its output said power-fail signal after a first delay;

f. second means for information storage having a first input leg electrically coupled to said output of said first means for delay and an output electrically coupled to a means for shutting down at least one power supply of said operating signal, said second means for information storage storing and providing at its output said power-fail signal when said power-fail signal appears at said input thereof;

g. means for detecting the shut-down of said power supply of said operating system, said means for detecting being electrically coupled to said power supply and providing at its output a power-off signal when said shut-down is detected, said output of said means for detecting being electrically coupled to said operating system;

h. means for generating a start-up signal electrically coupled to said output of said means for detecting, said means for generating providing at its output said start-up signal when said power-off signal appears at said output of said means for detecting;

i. a gate having first and second input legs, said first and second input legs thereof being electrically coupled to (i) said output of said means for comparison, and (ii) said output of said means for generating, respectively, said gate being adapted to provide at its output said start-up signal if and only if said power-recovery signal is present at said first input leg thereof contemporaneously with the presence of said start-up signal at said second input leg thereof;

said output of said gate being electrically coupled to a second input leg of each of said first and second means for information storage, said first and second means for information storage storing and providing at their respective outputs said power-recovery signal when said start-up signal appears at said output of said gate;

j. second means for delay electrically coupled to said output of said second means for information storage, said second means for delay providing at its output said power-recovery signal after a second delay, said output of said second means for delay being electrically coupled to said means for shutting down;

k. means for detecting the reactivation of said power supply of said operating system, said means for detecting said reactivation being electrically coupled to said power supply and providing at its output a power-on signal when said reactivation is detected;

l. third means for delay electrically coupled to said output of said means for detecting said reactivation, said third means for delay providing at its output said power-on signal after a third delay, said output of said third means for delay being electrically coupled to said operating system;

m. fourth means for delay electrically coupled to said output of said third means for delay, said fourth means for delay providing at its output said power-on signal after a fourth delay, said output of said fourth means for delay being electrically coupled to said operating system; and

n. a power source for said system, said power source deriving its power from said primary power source.

9. In a system for (i) shutting down the operation of an operating system when a primary power source which provides power to said operating system is in a power-fail condition and for (ii) starting up the operation of said operating system when said primary power source returns to a power-recovery condition, the combination comprising:

a. means for monitoring the voltage level of said primary power source;

b. means for detecting when said monitored voltage falls below the level of a reference voltage;

c. means for discriminating a power-fail condition from a transistory drop in the voltage level of said monitored voltage, said power-fail condition occuring when the level of said monitored voltage drops below that of said reference voltage and said drop in voltage persists for at least a first interval of time or recurs within a second interval of time;

d. means for providing a power-fail signal when said primary power source is in a power-fail condition;

e. means for providing a B+ control signal at a third interval following the appearance of said power-fail signal. f. means for providing a reset signaL substantially concurrently with said B+ control signal;

g. means for removing said power-fail signal when said primary power source is in a power-recovery condition, said power-recovery condition occurring when the level of said monitored voltage rises above that of said reference voltage;

h. means for removing said B+ control signal at a fourth interval following said removal of said power-fail signal, provided said power-recovery condition persists for said fourth interval;

i. means for removing said reset signal at a fifth interval following said removal of said B+ control signal;

provided said power-recovery condition persists for said fifth interval;

j. means for providing a restart at a sixth interval following said removal of said reset signal;

wherein said power-fail signal is adapted to provide to said operating system a warning that a power shut down will be carried out, said B+ control signal is adapted to shut down at least one power supply of said operating system, said reset signal is adapted to enable said operating system to lock itself into a non-operating mode, and said restart signal is adapted to enable said operating system to commence its operation.

10. The system of claim 9 having in addition thereto hold down means for substantially preventing the inadvertent removal of said power-fail signal or said B+ control signal by the electrical transient indicent to the loss of said primary source of power.