CIRCUIT ARRANGEMENT FOR SYNCHRONIZING TRANSMITTERS AND RECEIVERS IN DATA TRANSMISSION SYSTEMS

• US 3,761,891 A
• Filed: 03/17/1972
• Issued: 09/25/1973
• Est. Priority Date: 03/18/1971
• Status: Expired due to Term

• Current Assignee: Wernhard Markwitz
• Original Assignee: Wernhard Markwitz
• Inventors: Markwitz, Wernhard
• Primary Examiner(s): Atkinson, Charles E.
• Application Number:
  US05/235,680
• Time in Patent Office: 557 Days
• Field of Search: 340/146.1D 179/15 178/69.5
• US Class Current: 714/798
• CPC Class Codes: H04L 7/048 using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Abstract

A circuit arrangement for synchronizing transmitters and receivers in data transmission systems to facilitate the transfer of blocks of data constituted by information bits and parity bits is described. In the receiver the bits are serially entered into a shift register. A testing circuit is provided which, after supplying a testing clock signal, emits an output signal when the bits in the shift register pertain to the same data block. Testing circuits may be individually connected to stages in the shift register, and the testing signals are generated responsive to the presence of information or parity bits in the various register stages. Clock generators are provided for producing data block clock signals with as many block clock signals being produced as there are possible positions in the data blocks. The block clock signals are supplied to the testing circuits as testing clock signals via outputs of the clock generators. The testing circuit outputs are connected to counter inputs, and the counter outputs are connected to a logic circuit. The logic circuit determines the correct block clock signal in relation to the counter output signal.

Claims

1. A circuit arrangement for synchronizing transmitters and receivers in a data transmission system for accurately transmitting blocks of data, said blocks being constituted by information bits and parity bits, said bits, upon reception, being entered serially into a shift register, comprising:

a plurality of testing circuit means for supplying a testing clock signal and for thereafter producing a testing signal when bits are stored in said shift register which pertain to the same data block, said testing circuits being individually connected to different ones of the stages of said shift register, said testing circuits each including means for generating said testing signal responsive to information bits and parity bits, clock generator means for generating as many clock signals as there are bits in said data blocks, means for coupling said clock signals to said testing circuits, counter means having inputs connected to outputs of said testing circuits and logic circuit means connected to outputs from said counter for determining the correct block clock signal in relation to the output signals of said counter.

2. The circuit arrangement defined in claim 1 wherein as many as said testing circuits are provided as different block positions of said data blocks are possible, each said block clock signal being supplied to each said testing circuit, and wherein outputs of said testing circuits are connected to said counter means, said circuit arrangement additionally comprising second outputs of said testing circuits connected to reset inputs of said counter means.

3. The circuit arrangement defined in claim 1 wherein the outputs of said counter means are connected to reset inputs of said counter means over an OR gate.

4. The circuit arrangement defined in claim 1 additionally comprising:

bistable switching means to which the bits of said data blocks are supplied and which is connected to said shift register over an output, binary adder means having an input connected to an input of said bistable switching means and having a second input connected to an output of said bistable switching means, additional counter means constructed to have its registration increased by one unit when a counting signal appears at a first input, the additional counter means registration means being reset when a resetting signal appears at a second input, said addItional counter means being constructed further to transmit a counting signal over an output when a predetermined registration is reached, first gate means having inputs connected to said clock generator and to said adder, said output of said first gate being connected to said second input of said additional counter means, inverter means and second gate means having an input connected to the output of said adder over the said inverter means, said clock generator being connected to a second input of said second gate, the output of said second gate being connected to the first input of said additional counter means, and the output of said additional counter means being connected to the reset inputs of said counter means.

5. The circuit arrangement defined in claim 4 wherein a predetermined final position of registration of said additional counter means is lower in value than a predetermined final position of registration of said counter means.

6. The circuit arrangement defined in claim 1 further comprising:

first OR gate means, bistable switching means connected to outputs of said counter means, and additional input of said bistable switching means being connected to an output of said OR gate, AND gate means connected to outputs of said bistable switching means, each said block clock signal being supplied to each additional input of said AND gates, second OR gate means, outputs of said AND gates being connected to inputs of said second OR gate, and means connecting an output of said second OR gate to the output of said logic circuits.