LIGHT EMITTING DISPLAY ARRAY WITH NON-VOLATILE MEMORY

• US 3,763,468 A
• Filed: 10/01/1971
• Issued: 10/02/1973
• Est. Priority Date: 10/01/1971
• Status: Expired due to Term

• Current Assignee: Gordon R. Fleming, Stanford R. Ovshinsky
• Original Assignee: Gordon R. Fleming, Stanford R. Ovshinsky
• Inventors: Ovshinsky, Stanford R., Fleming, Gordon R.
• Primary Examiner(s): Pitts, Harold I.
• Application Number:
  US05/185,638
• Time in Patent Office: 732 Days
• Field of Search: 340/166EL,166R
• US Class Current: 345/76
• CPC Class Codes: G09F 9/33 being semiconductor devices, e.g. diodes
• CPC Class Codes: G09G 2300/0895 having more than one selection line for a two-terminal active matrix LCD, e.g. Lechner and D2R circuits
• CPC Class Codes: G09G 3/30 using electroluminescent panels
• CPC Class Codes: H04N 3/14 by means of electrically scanned solid-state devices for picture generation H04N25/00

Abstract

A light emitting display array which has a plurality of circuit lines in spaced apart relation to form a plurality of nonconnected junctures across each of which is connected a lightemitting circuit which is selectively activated between stable ON and stable OFF conditions to form a lighted display pattern. Each of the light-emitting circuits includes a light-emitting element connected in circuit with a non-volatile semi-conductor memory threshold switching device capable of being selectively activated between high resistance current blocking and low resistance current conducting conditions which remain permanently in the semiconductor material forming the memory threshold switching device even when power is removed therefrom or the polarity reversed. Where there exist a great difference in impedence between the moemory threshold switching device used and the particular light-emitting device connected thereto, there is provided a bridge circuit arrangement to compensate for such differences, and which includes threshold isolation means to prevent address signal information from activating undesired light emitting circuits. In the case where threshold isolation means is used it can take the form of a neon lamp or a gallium arsenide diode or the like and function as both the isolation means and the light emitting element. A display pattern can be formed on the display array either with or without operating potential applied thereto and the display array can be stored for indefinite periods of time without affecting the condition of the display pattern formed on the array.

Claims

1. A display array comprising:

a plurality of row circuit lines and a plurality of column circuit lines respectively having circuit junctures therealong to form pairs of circuit juncture points along different combinations of said row and column circuit lines across which juncture points memory element set and reset signal producing means are selectively connectable, a light control and emitting circuit associated with each of said pair of circuit juncture points and each including isolating and lightemitting means and a variable resistance memory element arranged in a circuit where said memory element is connected to the associated pair of circuit juncture points where memory element set and reset signals are applied through an impedance supplied by said means which isolates the same from the other memory elements of the array and where the associated said means and memory element are connectable to energizing voltage source means so the associated said means receives a light producing voltage or current when the associated memory element is in a light producing resistance condition, each of said variable resistance memory elements including memory material having at least two stable conditions respectively where the memory material has one stable structural condition where the resistance of the memory element is relatively high and a different structural condition where the resistance of the memory element is relatively low, said portions of variable resistance memory material including means capable of undergoing a stable reversible physical change in structure, by momentary application of energy thereto, selectively to either of said stable conditions by the signals of said memory set and reset signal producing means, said stable conditions persisting indefinitely after all signal sources have been removed therefrom, and each of said light - emitting means being related to the associated variable resistance memory element to receive said light producing voltage or current when said associated variable resistance memory material is in one of said stable conditions constituting a light producing condition and not to receive said light producing voltage or current when the variable resistance memory material of the associated memory element is in the other stable condition.

2. The display array of claim 1 wherein said isolating and light-emitting means associated with each pair of circuit juncture points is a single element which supplies said isolating impedance and produces said light.

3. The display array of claim 1 wherein said isolating and light-emitting means associated with each pair of circuit juncture points are a pair of elements, one of which produces light but has such a small impedance as not to supply said isolating impedance and the other element is an element supplying said isolating impedance.

4. The display array of claim 1 wherein there is provided switching means for selectively connecting said memory element set and reset signal producing means to a selected one of said row circuit lines and to a selected one of said column circuit lines to apply the same to a selected pair of juncture points.

5. The display array of claim 4 wherein only the memory element and isolating element associated with each pair of circuit juncture points is connected in series across such pair of juncture points, said memory element and light producing means associated with each pair of circuit juncture points being connectable to said energizing voltage source means through an energizing circuit which does not include said isolating element.

6. The display array of claim 5 wherein said energizing circuit is a bridge circuit having one arm including said memory element and three other arms excluding the associated light producing means, the bridge circuit having energizing voltage input terminals to which said energizing voltage source means is applied and a pair of output terminals across which no voltage appears when the bridge circuit is in a balanced condition and across which an output appears when the bridge circuit is unbalanced, the light producing means associated with each pair of circuit functure points being connected across said output terminals of the bridge circuit, and said bridge circuit being unbalanced only when said memory element is in said light producing condition.

7. The display array of claim 6 wherein the resistance of each memory element in its high resistance condition is substantially less than the impedance of said light producing means.

8. The display array of claim 1 wherein the memory and light-emitting means associated with each pair of circuit juncture points are connected in series circuit relation when said energizing voltage source means is connected thereto, and wherein the light-emitting means receives a light-emitting current or voltage only when the associated memory element is in its low resistance condition.

9. The display array of claim 1 wherein each of said light-emitting means is an electroluminescent element.

10. The display array of claim 1 wherein the isolating and light-emitting means of each light control and Emitting circuit associated with each pair of circuit juncture points is a single threshold-type element which emits light when the voltage applied thereto exceeds a given threshold voltage level which ocurrs when the associated memory element is said light producing condition.

11. The display array of claim 4 wherein said isolating and light-emitting means of each light control and emitting circuit associated with each pair of circuit juncture points is a single capacitive element where the capacitance of the element is sufficient to form isolation between said memory elements when said set signal is a relatively slowly rising signal where the capacitive element does not act as a short circuit for the set signal.

12. A display array comprising a plurality of spaced, light-emitting elements each of which is to produce a visible light at an observation point in front of the array when the same is supplied with energizing voltage, a variable impedance memory element associated with each light-emitting element, each variable impedance memory element having a stable high impedance condition which is changeable to a stable low impedance condition by the momentary application thereto of a memory element setting signal, and being resettable back to its stable high impedance condition by the momentary application thereto of a memory element resetting signal, the high impedance of each memory element supplying an impedance smaller than the impedance of the associated light-emitting element, whereby the memory element acts as an ineffective switch for controlling the application of energizing to the associated light-emitting element if connected in a simple series circuit between a source of energizing voltage and the associated light-emitting element, means for selectively feeding memory element setting and resetting signals to any memory element associated with any one of said light-emitting elements, and circuit-forming means for supplying energizing voltage to each of said light-emitting elements under the control of the impedance condition of the associated memory element each of said circuit-forming means forming with each memory element a bridge circuit having a pair of input terminals across which energizing voltage for the light-emitting element is applied and a pair of output terminals across which appreciable energizing voltage appears only when the bridge circuit is unbalanced, each of said light-emitting elements being connected across the output terminals of the associated bridge circuit, the bridge circuit being balanced when the associated memory element in one of said stable impedance conditions and being unbalanced when the associated memory element is in its other stable impedance condition.

13. The display array of claim 12 wherein each of said bridge circuit-forming means includes a first branch with said memory element and an impedance means connected in series across the input terminals of the bridge circuit and another branch in parallel with said first branch and comprising a center-tapped secondary winding of a transformer having a primary winding connectable to a source of AC voltage, said output of said bridge circuit being between the center tap of said secondary winding of said transformer and the juncture between said memory element and said impedance means.

14. The display array of claim 1 wherein the memory element, light producing element and the isolating element are connected in series between the associated pair of circuit juncture points.

15. The display array of claim 3 wherein each isolating element is a two terminal threshold device which is operated in a low resistance condition when a voltage of any polarity in excess of a given voltage is applied thereto.