TRAFFIC SIGNAL CONTROL DEVICE

• US 3,764,973 A
• Filed: 04/14/1971
• Issued: 10/09/1973
• Est. Priority Date: 04/14/1970
• Status: Expired due to Term

• Current Assignee: Akira Muramatu, Tatsuro Ichihara
• Original Assignee: Akira Muramatu, Tatsuro Ichihara
• Inventors: Ichihara, Tatsuro, Muramatu, Akira
• Primary Examiner(s): Cooper, William C.
• Application Number:
  US05/133,882
• Time in Patent Office: 909 Days
• Field of Search: 340/40
• US Class Current: 340/915
• CPC Class Codes: G08G 1/081 Plural intersections under common control

Abstract

A traffic signal control device for applying signals for switching signals at a multiplicity of intersections. The traffic signal control device comprises a core memory in which a group of variable data such as elapsed times, steps and traffic information, a group of fixed data such as initial portions, unit extensions and maximum green signal periods, and a group of instruction data are stored; a pulse generator for generating pulses for varying the values of the variable data; and a control means for incrementing the data of elapsed time, comparing the incremented data to a corresponding fixed data, and incrementing the data of step when the value of the elapsed time equals with the corresponding fixed data.

Claims

1. A traffic signal control device comprising a core memory having a memory area for storing data representative of elapsed time, traffic information, unit extensions and a group of instruction data;

a pulse generator means; and

a control means operable in response to each output signal from said pulse generator means, to increment said data which indicates said elapsed time, and which is stored in said core memory, by a certain number, to compare said incremented data to said data representative of unit extension time for the green period of a light and to generate, when said incremented data is in coincidence with said data representative of unit extension time, step advancing signals for changing the indication of traffic signal lights.

2. A traffic signal control device according to claim 1, wherein a register, in which data indicating elapsed time and data indicating unit extension time, corresponding to each of a plurality of intersections, is stored, and means for selecting one of said intersections is further provided, and said unit extension time for the green period and said data indicating elapsed time corresponding to one of said intersections selected by said means are read out and compared with each other by said control device.

3. A traffic signal control device according to claim 2, wherein said data and which is stored in said register, is successively incremented by a certain number in response to the output of said pulse generator.

4. A traffic signal control apparatus comprising:

a core memory for storing digital data representative of information for controlling traffic signals, including variable data corresponding to elapsed times and traffic flow, fixed data corresponding to the initial minimum green period of a traffic signal, unit extensions and maximum signal priorities corresponding to a prescribed traffic intersection condition, and instruction data;

first means coupled to said core memory, for writing therein and reading out therefrom at least a portion of said digital data;

a pair of data conveying paths, for transmitting data to be stored within said read out from said memory, whereby control signals may be supplied to said traffic signals for actuation thereof;

second means for generating a sequence of control pulses; and

third means, responsive to each of the pulses in said sequence of pulses produced by said second means, for incrementing the data in said core memory corresponding to elapsed times by a predetermined number, for comparing said data which has been incremented with said data indicating unit extension time stored in said memory, and for generating step advancing signals for changing the indication of traffic signal lights when said incremented data coincides with said data indicating unit extension time.

5. An apparatus in accordance with claim 4, wherein said third means comprises a program control circuit, responsive to said second means, for controlling the time occurrence of operation of said apparatus.

6. An apparatus according to claim 5, further including a first register connected to a first of said pair of data conveying paths, for storing therein the data in said first path for controlling the operation of said program control circuit.

7. An apparatus according to claim 6, further including a memory address register, coupled to the second of said pair of data paths for controlling the selection of a data storage position within said core memory, said first means including respective read-out and write in amplifiers coupled to said core memory, and further including a read out memory register for transferring data from said core memory to said first data path.

8. An apparatus according to claim 7, further including a first gate circuit, coupled to the output of said read-out memory register and responsive to said program control circuit for contrOllably gating data within said memory to said first data conveying path, and further including a second gate circuit, a first adder and a third gate circuit, connected in series between the output of said read-out memory register and said first conveying path, each of said gate circuits being responsive to said program control circuit.

9. An apparatus according to claim 8, further including a fourth gate circuit, responsive to said program control circuit, for updating the count of said first adder in response to a first increment signal from said program control circuit, and a first adder register, which stores a predetermined portion of the data in said first path, the output of which is controllably gated to said first adder.

10. An apparatus in accordance with claim 9, wherein said third means further includes a second adder circuit, controllably gated to pass data from said first to said second data paths, and having a pair of incrementing inputs connected to first and second up count gate circuits, for incrementing the data in said second adder by a second and third predetermined number, in response to said program control circuit.

11. An apparatus in accordance with claim 10, further including an incrementing storage register for storing the data in said second conveying path, the output of said incrementing storage register being controllably gated by said program control circuit to said first data conveying path, and a discriminator circuit, responsive to the output of said incrementing storage register, and being controllably gated to said first and second up count gate circuits, for incrementing the count in said second adder by said second and third predetermined numbers in response to first and second predetermined conditions of the contents of said incrementing storage register.

12. An apparatus in accordance with claim 11, further including a complementing circuit gateably connected between said first data conveying path and said second adder.

13. An apparatus in accordance with claim 12, further including an LNR register and an IC register, gateably coupled between said second and first data conveying paths for transferring respective specified portions of the data in said second path to said first path for transmission to said first register.