CARRIER DETECTION CIRCUIT

• US 3,766,479 A
• Filed: 10/04/1971
• Issued: 10/16/1973
• Est. Priority Date: 10/04/1971
• Status: Expired due to Term

• Current Assignee: David Arthur Thalimer, Myungsae Son
• Original Assignee: David Arthur Thalimer, Myungsae Son
• Inventors: Thalimer, David Arthur, Son, Myungsae
• Primary Examiner(s): Mayer, Albert J.
• Application Number:
  US05/186,362
• Time in Patent Office: 743 Days
• Field of Search: 178/66,88 325/30,320,474,64 329/104
• US Class Current: 375/334
• CPC Class Codes: H04L 1/206 for modulated signals
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits

Abstract

A carrier detection circuit for use with a modem receiver wherein noise level on the circuit is compared to the level of carrier to turn on a latch circuit, and turning off the latch circuit is controlled by comparing the output of an automatic gain control circuit responsive to carrier plus noise level to circuit noise level. A time delay in the automatic gain control circuit prevents turn-off due to momentary signal drop-outs.

Claims

1. A frequency shift keyed receiver having a carrier detection circuit for detecting the presence of a received signal, said carrier detection circuit comprising:

A. a carrier detect latch circuit;

B. first comparing means for setting said latch circuit, said first comparing means including;

1. first filter means responsive to received signals for eliminating carrier energy from said received signals leaving line noise, 2. second filter means passing only mark frequency energy in the received signal, and 3. a first comparator connected to the respective outputs of said first and second filter means; and

C. second comparing means for resetting said latch circuit.

2. a gate circuit having a first input connected to the frequency shift keyed receiver, a second input connected to said output of said bistable circuit, and an output terminal;

B. first filter means adapted to be connected to received signals for eliminating frequency shift keyed signals;

C. second filter means adapted to be connected to received signals for passing mark signals;

D. a first comparator in circuit with said first and second filter means;

E. signal level responsive means adapted to be connected to received signals;

F. second comparator means in circuit with said first filter means and said signal level responsive means; and

G. means interconnecting said first and second comparator means with said carrier detect latch circuit.

3. a first comparator connected to the respective outputs of said first and second filter means;

and C. second comparing means for resetting said latch circuit.

4. In a carrier detection circuit for use in connection with a frequency shift keyed receiver, the combination of:

A. a carrier detect latch circuit, said carrier detect latch circuit including;

5. In the carrier detection circuit of claim 4, said first filter means including:

a first band elimination filter tuned to reject the space frequency; and

a second band elimination filter tuned to reject the mark frequency.

6. In the carrier detection circuit of claim 5, said second band elimination filter being connected in series relation with said first band elimination filter.

7. In the carrier detection circuit of claim 6, said second filter means including a band pass filter tuned to pass the mark frequency connected in series relation with said first band elimination filter.

8. In the carrier detection circuit of claim 7, said first comparator means including:

first rectifying means connected to said second band elimination filter to provide a direct voltage proportional to noise;

second rectifying means connected to said band pass filter to provide a direct voltage proportional to mark signals; and

a first voltage comparator connected to said first and second rectifiers to provide an output voltage proportional to the mark signal to noise ratio to the set terminal of said bi-stable circuit.

9. In the carrier detection circuit of claim 8, said signal level responsive means including an automatic gain control circuit.

10. In the carrier detection circuit of claim 9, said second comparator means including:

a third rectifying means connected to said automatic gain control circuit to provide a voltage proportional to received signal; and

a second voltage comparator connected to said first rectifying means and said third rectifying means to provide an output voltage proportional to the signal to noise ratio to the reset terminal of said bi-stable circuit.