SCHOTTKY BARRIER TYPE FIELD EFFECT TRANSISTOR

• US 3,767,984 A
• Filed: 09/13/1972
• Issued: 10/23/1973
• Est. Priority Date: 09/03/1969
• Status: Expired due to Term

• Current Assignee: Daizaburo Shinoda, Nobuo Kawamura
• Original Assignee: Daizaburo Shinoda, Nobuo Kawamura
• Inventors: Shinoda, Daizaburo, Kawamura, Nobuo
• Primary Examiner(s): Edlow, Martin H.
• Application Number:
  US05/288,903
• Time in Patent Office: 405 Days
• Field of Search: 317/235B,235U,235R,234R
• US Class Current: 257/268
• CPC Class Codes: H01L 27/00 Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate details thereof H01L23/00, H01L29/00 - H10K10/00; assemblies consisting of a plurality of individual solid state devices H01L25/00
• CPC Class Codes: H01L 29/00 Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor H01L31/00 - H01L33/00, H10K10/00, H10N take precedence; details other than of semiconductor bodies or of electrodes thereof H01L23/00; devices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00
• CPC Class Codes: Y10S 148/056 Gallium arsenide
• CPC Class Codes: Y10S 148/139 Schottky barrier

Abstract

A Schottky barrier gate field effect transistor is capable of operating in the enhancement mode. The transistor includes a gallium arsenide layer formed on a substrate. The relationship between the thickness W and impurity concentration N of the gallium arsenide layer is given by the expression: 2 X 103CM 1/2 < W . square root N < 3 X 103 cm 1/2.

Claims

1. A Schottky barrier gate field effect transistor comprising a substrate of high resistivity, an n-type gallium arsenide layer formed on said substrate;

source and drain electrodes attached to said gallium arsenide layer, and a gate electrode formed on a portion of the surface of said gallium arsenide layer between said source and drain electrodes, said gate electrode being made of a metal selected from the group consisting of aluminum, gold, nickel and chromium, said gallium arsenide layer having an impurity concentration ranging from 1 X 1015cm 3 to 1 X 1016cm 3 and a thickness meeting the condition given by 2 X 103cm 1/2<

W . square root N <

3 X 103cm 1/2 where N and W represent, respectively, said impurity concentration and the thickness of said gallium arsenide layer measured at the portion of said layer lying beneath said gate electrode, whereby said field effect transistor is enabled to function in the enhancement mode.

2. A Schottky barrier gate field effect transistor comprising a substrate of high resistivity, an n-type silicon layer formed on said substrate, source and drain electrodes attached to said silicon layer, and a gate electrode formed on a portion of the surface of said n-type silicon layer between said source and drain electrodes, said gate electrode being made of a material selected from the group consisting of molybdenum, platinum, gold, palladium, platinum silicide and palladium silicide, wherein said silicon layEr has an impurity concentration ranging from 1 X 1016cm 3 to 5 X 1016cm 3 and a thickness meeting the condition given by 2 X 103cm 1/2<

W . Square Root N <

3 X 103cm 1/2 where N and W represent, respectively, said impurity concentration and the thickness of said silicon layer measured at the portion of said layer lying beneath said gate electrode, whereby said field effect transistor is enabled to function in the enhancement mode.

3. The transistor as claimed in claim 2, wherein said gate electrode is made of platinum silicide and wherein the thickness of the portion of said semiconductor layer lying beneath said gate electrode is in the range from 0.15 Mu to 0.3 Mu .