SIGNAL REGENERATOR CIRCUIT FOR PAGING RECEIVER

• US 3,768,090 A
• Filed: 03/08/1972
• Issued: 10/23/1973
• Est. Priority Date: 03/08/1972
• Status: Expired due to Term

• Current Assignee: Ronald O. Williams
• Original Assignee: Ronald O. Williams
• Inventors: Williams, Ronald O.
• Primary Examiner(s): Pitts, Harold I.
• Application Number:
  US05/232,882
• Time in Patent Office: 594 Days
• Field of Search: 307/268R 340/167A,164R,311R
• US Class Current: 340/7.32
• CPC Class Codes: H04W 88/027 using frequency address codes

Abstract

A signal regenerator circuit for a selective paging receiver utilizes a differential amplifier to derive from a received subscriber address-bearing code signal a level-equalized code signal suitable for application to the receiver decoding circuitry. To make the width of the individual bits of the derived code signal independent of the received signal amplitude, an amplitude-dependent control voltage is applied to the differential amplifier to vary the slicing level of the amplifier with variations in signal amplitude. A clamping circuit is provided to stablize the slicing level, and a capacitor discharge circuit is provided to prevent low-frequency DC skewing by the large interstage coupling capacitance employed in the regenerator circuit.

Claims

1. In a selective paging receiver of the type having a power supply periodically activated for a short time period to energize the components of said receiver for enabling said receiver to receive and recognize a low frequency code signal formed from a plurality of serially received bits and amplified by a first amplifier for application to a signal regenerator circuit comprising:

first and second transistors each having a base circuit, a collector circuit and an emitter circuit;

a common impedance connected in series with each emitter circuit to define a differential amplifier configuration for said first and second transistors;

a third transistor having a base circuit coupled to the collector circuit of said first transistor with said third transistor operated in saturation in response to signals above a predetermined level appearing in said first transistor collector circuit for transmitting constant amplitude signals each corresponding to the width of said bits;

a fourth transistor having an emitter circuit coupled to the base circuit of said second transistor;

means including a capacitor interconnected between the output of said first amplifier and a pair of serially connected unidirectional circuit elements coupled to the base circuit of said fourth transistor for transmitting to said fourth transistor base circuit a d.c. signal corresponding to the amplitude of each said received bit to control the conduction level of said first transistor, for controlling the width of each signal transmitted by said third transistor;

another capacitor having a large time constant connected between the output of said first amplifier and said first transistor base circuit for transmitting a signal corresponding to each bit to said first transistor base circuit for enabling said first transistor to conduct for each received bit;

first clamp means connected between said other capacitor and said first transistor base circuit for ensuring each signal transmitted by said other capacitor to said first transistor base circuit has a predetermined minimum amplitude whereby said first transistor conducts only in response to the signal transmitted by said other capacitor having said minimum amplitude; and

other means connected intermediate said other capacitor and said first clamp means rendered momentarily conductive in response to each activation of said power supply for enabling said large time constant other capacitor to transmit a signal corresponding to said minimum amplitude substantially simultaneously with said activation.

2. The circuit claimed in claim 1 in which said first clamp means comprises a last transistor having a base, emitter and collector circuits, a plurality of serially connected unidirectional circuit elements connected between the base circuit of said last transistor and one terminal of said battery to establish a fixed voltage thereat for controlling the emitter voltage of said last transistor, and a last unidirectional circuit element interconnecting said other capacitor and said last transistor emitter circuit to shunt any signal below said emitter voltage from said first transistor base circuit.

3. The circuIt claimed in claim 2 in which said other means comprises a shunt transistor having a base, emitter and collector circuits with said shunt transistor collector circuit connected intermediate said other capacitor and said last unidirectional circuit element, and a last capacitor connected intermediate said shunt transistor base circuit and said power supply for rendering said shunt transistor momentarily conductive in response to activation of said power supply to discharge said other capacitor through said shunt transistor emitter circuit.