DIGITAL INDICATOR WITH MEANS FOR SUPPRESSING LEAST SIGNIFICANT DIGIT DITHER

• US 3,769,583 A
• Filed: 03/15/1971
• Issued: 10/30/1973
• Est. Priority Date: 03/15/1971
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Arthur R. Winter, Richard B. Spencer
• Inventors: Spencer, Richard B., Winter, Arthur R.
• Primary Examiner(s): Smith, Alfred E.
• Application Number:
  US05/124,091
• Time in Patent Office: 960 Days
• Field of Search: 324/78,186,72,129 328/140,72
• US Class Current: 324/76.64
• CPC Class Codes: G01R 23/10 by converting frequency into a train of pulses, which are then counted , i.e. converting the signal into a square wave
• CPC Class Codes: H03M 1/60 with intermediate conversion to frequency of pulses

Abstract

A digital indicator comprising a counter for providing digital representations of the frequency of an input signal. The input signal is applied to the counter through a gate responsive to a periodically occurring timing pulse. The timing pulse is derived from a second counter that receives fixed frequency clock pulses through a second gate. Synchronizing means, responsive to the input signal, operate the second gate whereby the timing pulse is controlled to occur in timed relation to the input signal.

Claims

1. An indicator for providing digital representations of the frequency of an input signal comprising counting means for providing said digital representations, timing means for providing a timing pulse of predetermined duration, gating means connected to receive said input signal and said timing pulse for transmitting said input signal to said counting means during said duration of said timing pulse, and synchronizing means connected to receive said input signal for initiating said timing pulse in timed relation to said input signal, wherein said timing means comprises a source of cyclic signal and further counting means coupled through said synchronizing means to receive said cyclic signal for providing said timing pulse in accordance with predetermined counts thereof, wherein said synchronizing means comprises bistable means providing first and second control signals in accordance with the first and second states thereof, respectively, further gating means coupled to receive said cyclic signal and said first control signal for transmitting said cyclic signal to said further counting means in response to said first control signal and additional gating means coupled to receive only said input signal and said second control signal for transmitting said input signal to said bistable means in response to said second control signal for setting said bistable means to said first state, said further counting means providing a signal representative of a predetermined count thereof coupled to said bistable means for resetting said bistable means to said second state.

2. The indicator of claim 1 in which said further counting means comprises a first pulse counter coupled to receive said cyclic signal transmitted through said further gating means for providing first digital count signals in response thereto, and decoding means coupled to receive said first digital count signals for providing said timing pulse and a latch pulse thereafter in response to predetermined counts of said first pulse counter.

3. The indicator of claim 1 in which said counting means comprises a second pulse counter coupled to receive said input signal transmitted through said gating means for providing second digital count signals in response thereto, buffer storage means coupled to receive said second digital count signals and said latch pulse for storing the instantaneous values of said second digital count signals in response to said latch pulse, and readout means coupled to said buffer storage means for providing said digital representations of said frequency of said input signal in accordance with said stored instantaneous values of said second digital count signals.

4. The indicator of claim 3 in which said readout means comprises converter means coupled to said buffer storage means for converting said stored second digital count signals to signals representative of decimal digits, and decimal digit indicator means responsive to said decimal digit signals for displaying said decimal digits thereby providing said digital representations of said frequency of said input signal.

5. The indicator of claim 3 in which said decoding means includes means for providIng a reset pulse after said latch pulse to reset said second pulse counter to a reference state.