SOLID STATE ACCELERATION COUNTER

• US 3,769,844 A
• Filed: 04/29/1971
• Issued: 11/06/1973
• Est. Priority Date: 04/29/1971
• Status: Expired due to Term

• Current Assignee: Alexander E. Skoures
• Original Assignee: Alexander E. Skoures
• Inventors: Skoures, Alexander E.
• Primary Examiner(s): Wilbur, Maynard R.
• Assistant Examiner(s): Thesz, Jr., Joseph M.
• Application Number:
  US05/138,516
• Time in Patent Office: 922 Days
• Field of Search: 235/92AE,92CA,92PB 73/88.5R,91,517R,489
• US Class Current: 377/23
• CPC Class Codes: G01P 15/036 for indicating predetermined acceleration values
• CPC Class Codes: G01P 15/08 with conversion into electric or magnetic values

Abstract

An accelerometer mounted to an aircraft structure supplies an electrical signal to a low-pass filter in which all frequencies above 2.5 Hz are attenuated. The signal from the filter is applied to a timing circuit wherein a switch is actuated if the applied signal exceeds a preset amplitude for a predetermined period of time. The output signal of the filter is also applied to a plurality of voltage comparators of various settings in which respective output signals are generated if the filter output signal exceeds various predetermined setpoints. The coincidence of outputs from the timing circuit and an individual voltage comparator pulses a counter associated with the comparator and advances the counter one unit to record the fact that a load factor level above a predetermined magnitude has been experienced by the aircraft.

Claims

1. An acceleration counter comprising:

transducer means for providing an electrical signal indicative of a magnitude of a load;

a low-pass filter connected to said transducer means for conducting an electrical signal below a predetermined frequency;

first comparator means connected to receive the low-pass filter signal for providing an output signal when the filter signal exceeds a predetermined level;

timing means connected to said first comparator means for providing an output signal when the duration of the first comparator means output signal exceeds a predetermined period of time;

second comparator means connected to receive the low-pass filter signal for providing at least one output signal when the filter signal exceeds at least one of a plurality of predetermined levels;

first gating means including a plurality of silicon controlled rectifiers having anode electrodes parallelly connected to receive the timing means output signal and gate electrodes connected to receive respective ones of said second comparator means output signals for first conducting the timing means output signal upon coincidence of the timing means output signal and respective ones of said second comparator means output signals and for continuing to conduct the timing means output signal in the absence of the second comparator means output signals; and

counting means connected to receive the timing means output signal from said first gating means for advancing one count on receipt of the timing means output signal.

2. An acceleration counter according to claim 1 wherein said tIming means further comprises:

switching means adapted to receive a bias signal and connected to said first comparator means for providing an output signal upon receipt of a first comparator means output signal;

oscillation means connected to said switching means for providing an output signal upon receipt of said switching means output signal for a predetermined period of time; and

second gating means connected to said switching means and said oscillation means for conducting the switching means output signal upon receipt of the oscillation means output signal and continuing to conduct until removal of the switching means output signal.

3. An acceleration counter according to claim 2 wherein said second gating means further comprises:

a silicon controlled rectifier having an anode connected to receive the switching means output signal, a gate connected to receive the oscillation means output signal and a cathode for providing an output signal upon coincidence of said oscillation means output signal and the switching means output signal and then continuing to provide an output signal so long as said switching means output signal persists.

4. An acceleration counter according to claim 3 wherein said oscillation means further comprises a relaxation oscillator circuit.

5. An acceleration counter according to claim 4 wherein said switching means further comprises:

a first transistor having a base electrode connected to said first comparator means, a collector electrode adapted to receive the bias signal and an emitter electrode grounded for conducting the bias signal upon receipt of an output signal from said first comparator means;

a second transistor having a base electrode connected to said first transistor'"'"''"'"'s collector electrode, an emitter electrode connected to receive said bias voltage and a collector electrode having an output terminal connected for providing conduction for said bias signal upon said first transistor conducting; and

a grounded resistor connected to said second transistor'"'"''"'"'s collector electrode.

6. An acceleration counter according to claim 5 wherein said first transistor is an NPN junction transistor and said second transistor is a PNP junction transistor.

7. An acceleration counter according to claim 6 wherein said first comparator means further comprises:

a differential amplifier with a first input connected to receive the low-pass filter signal and a second input adapted to receive a reference level signal and providing an output when the low-pass filter signal exceeds the reference signal level.

8. An acceleration counter according to claim 7 wherein said second comparator means further comprises:

a plurality of voltage divider circuits adapted to receive an input signal and for providing output signals of various predetermined levels; and

a plurality of differential amplifiers with a first input connected to receive the low-pass filter signal and a second input connected to receive respective voltage divider output signals so that each respective differential amplifier provides an output signal when the low-pass filter signal is in excess of its respective voltage divider output signal.