OPERATING CONDITION MONITORING IN DIGITAL COMPUTERS

• US 3,771,131 A
• Filed: 04/17/1972
• Issued: 11/06/1973
• Est. Priority Date: 04/17/1972
• Status: Expired due to Term

• Current Assignee: Andrew T. Ling
• Original Assignee: Andrew T. Ling
• Inventors: Ling, Andrew T.
• Primary Examiner(s): Henon, Paul J.
• Assistant Examiner(s): Thomas, James D.
• Application Number:
  US05/244,397
• Time in Patent Office: 568 Days
• Field of Search: 340/146.1,172.5 235/153 324/73
• US Class Current: 714/45
• CPC Class Codes: G06F 11/25 Testing of logic operation, e.g. by logic analysers

Abstract

In a stored program digital computer, which includes memory, CPU and input/output equipment, and having a plurality of hardwired test points developing signals during operation of computer from which particular test points are selected. Upon execution of a selectable instruction by the CPU and in timed response to a preselected clock phase during the instruction, the signals as developed by the selected test points are received to provide an operational '"'"''"'"''"'"''"'"'snapshot'"'"''"'"''"'"''"'"' of the computer.

Claims

1. In a stored program digital computer, which includes memory, CPU and input/output equipment, for carrying out computing programs by executing instructions, there being data paths in the computer through which flow data pursuant to regular operation of the computer, the execution of instructions being carried out in steps defined by clock phases, the improvement of a monitoring system for the computer for monitoring operation without intervention and interruption of execution of an instruction, comprising:

a plurality of n X w test points in at least a portion of the computer circuit, each of the test points developing signals during operation of the computer, n and w being positive integers;

plural connecting hardwired test lines, permanently connected to the test points separately from any said data paths in the computer;

first means connected to said connecting hard-wired lines and provided for selecting w particular ones of the test points and including selectively operating switching means for obtaining the selecting of the particular ones of the test points;

second means including a register connected to the first means and provided for receiving the w signals as developed by the w test points and as selected by the first means and temporarily storing the w signals as an assembly of w unrelated bits;

third means connected to be responsive to a preselected phase in the operation of the computer including means (a) for being responsive to execution of a selectable instruction by the CPU; and

means (b) for being responsive to a preselected clock phase in the execution of the selectable instruction when executed for determining said operation phase; and

fourth means connected for enabling the second means so that the register of the second means receives said developed signals at the instance of response of the means (a) and of the means (b).

2. In a computer as in claim 1, whereby the means (a) is responsive to a memory address when called on by the CPU as holding an instruction during which the phase is to occur.

3. In a computer as in claim 1, including means for controlling selection of the test points by the first means.

4. In a stored program, digital computer which includes memory, CPU and input/output equipment and having a plurality of registers, the CPU including means responsive to particular instructions for loading specified registers of the plurality of registers, the CPU further including means for being responsive to other instructions for reading specified registers of the plurality of registers, the CPU further including means for performing counting and count number testing operations, the improvement of a monitoring system operating independently from regular computer operation, comprising:

a plurality of n X w test points in at least a portion of the computer circuit, each of the test points developing signals at different levels during operation of the computer, n and w being positive integers;

plural connecting hardwired test lines permanently connected to the test points and holding signals representing the respective signal level at these test points;

a select matrix connected to said connecting test lines, and having n selection lines respectively for selecting n groups of w connecting lines each, and out of said n X w connecting lines, further having w output lines holding the signals of the group of the respectively selected test lines;

first means including a first register of the plurality of registers and connected for selecting one out of said n selection lines in dependence upon the content of the first register;

a second register of the plurality for receiving the signal content of the w output lines;

second means connected to be responsive to the progressing phases of execution of any instruction by the computer;

a counter connected to the second means to count the said progressing phases of an instruction when executed;

third means responsive to the counter having reached a particular count state to provide a timing signal;

gating means connected in-between the output lines of the select matrix and said second register and further connected to receive said timing signal for setting the content of the said output lines into the second register in representation of the individual signal levels of those test points which are connected to the respective selected ones of the test lines;

said computer operating to read the second register subsequently and further operating to update the content of the first register to change the selection from among the n selection lines and connecting lines accordingly; and

means for selecting a particular instruction which, when executed, causes the third means to provide the timing signal when the counter reached the particular count state during execution of the selected particular instruction.

5. In a computer as in claim 4, the third means including a third register, the computer operating to update the content of the third register, the third means further including means to transfer the content of the third register to said counter.