MEMORY DEVICE HAVING MAIN SHIFT REGISTER AND SUPPLEMENTARY SHIFT REGISTER

• US 3,771,133 A
• Filed: 09/06/1972
• Issued: 11/06/1973
• Est. Priority Date: 09/11/1971
• Status: Expired due to Term

• Current Assignee: Toshio Kashio
• Original Assignee: Toshio Kashio
• Inventors: Kashio, Toshio
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Woods, Paul R.
• Application Number:
  US05/286,845
• Time in Patent Office: 426 Days
• Field of Search: 340/172.5
• US Class Current: 711/109
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers

Abstract

A memory device including a buffer register for storing input data and a main shift register having addresses arranged in series so as to store input data supplied from said buffer register in a specified address, wherein, in case input data being stored in the main register has more digits than those initially designed for the prescribed address of the main shift register, there is serially connected to the main shift register a supplementary shift register capable of handling numerous digits so as to store said excess digits as a temporary extension of the capacity of the main shift register. There is formed a path of circulatory shifting between the input section of the main shift register and the position of the least significant digit which is detected by detecting means to have flowed over to said supplementary shift register when the specified address of the main shift register is fully filled with inputs from the buffer register and there is connected between the main shift register and supplementary shift register means for disconnecting the supplementary shift register from the main shift register at the beginning of cycle of circulatory shifting in said main shift register.

Claims

1. A memory device comprising:

a buffer register for storing input data;

a main shift register for storing in specified addresses input data from said buffer register in the form of serially arranged words by use of word dividing codes inserted into each address;

a supplementary shift register serially connected to said main shift register for temporarily stoRing excess digits when the input data from said buffer register has more digits than those already registered in the addresses of said main shift register, the already registered digits corresponding to the storage capacity of said main shift register;

by-pass means for feeding back data of said excess digits registered in said supplementary shift register to an input terminal of said main shift register when input data from said buffer register has been fully filled in the addresses of said main shift register; and

disconnecting means coupled to said by-pass means for disconnecting said supplementary shift register from said main shift register by rendering said by-pass means inoperative in a particular timing corresponding to each cycle of circulatory shifting in said main shift register.

2. A memory device according to claim 1 wherein said by-pass means comprises a ring counter for counting digits and AND circuits coupled thereto, said AND circuits being responsive to the outputs from said ring counter and outputs corresponding to said excess digits from said supplementary shift register to form gate input signals.

3. A memory device according to claim 1 wherein said disconnecting means comprises a mark signal detecting means comprises a mark signal detecting means coupled to said main shift register and adapted to render said by-pass means inoperative responsive to detection of a given mark signal.

4. A memory device according to claim 1 wherein said by-pass means includes means responsive to detection of at least a start code in the stored data to render said bypass means inoperative.