MEMORY CONTROL IN A MULTIPURPOSE SYSTEM UTILIZING A BROADCAST

• US 3,771,137 A
• Filed: 09/10/1971
• Issued: 11/06/1973
• Est. Priority Date: 09/10/1971
• Status: Expired due to Term

• Current Assignee: Jan Gustav Oblonsky, John Anton Deveer, Robert Paul Barner
• Original Assignee: Jan Gustav Oblonsky, John Anton Deveer, Robert Paul Barner
• Inventors: Barner, Robert Paul, Deveer, John Anton, Oblonsky, Jan Gustav
• Primary Examiner(s): Henon, Paul J.
• Assistant Examiner(s): Sachs, Michael
• Application Number:
  US05/179,376
• Time in Patent Office: 788 Days
• Field of Search: 340/172.5
• US Class Current: 711/120
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)

Abstract

In a multiprocessing computer where a plurality of processors, each with its own buffer memory, share a main memory, a broadcast system provides each processor the capability to query each other processor to determine whether a modified (e.g. updated) version of the desired data is located in another processor'"'"''"'"'s buffer memory. The memory control unit simultaneously initiates a main memory read cycle and a broadcast signal in response to a request for data. If a modified version of the data is found to be in a buffer memory, it is transferred to the main memory by the control unit. The main memory read cycle is then changed to a write cycle so that the modified version replaces the original data. The modified data is then switched onto the memory data bus and transmitted to the requesting processor. Using this system, which only allows one buffer to contain a modified version of any data item, the requesting processor obtains the most current data in one main memory cycle in such a manner that it appears that the data is originating from main memory.

Claims

1. A memory control system in a data processing system with a main memory and a plurality of data processors, each processor having the capability to modify data, and including its own buffer memory unit in which to retain data comprising:

system control means;

circuit means associated with said control means for selectively connecting said main memory to each of said plurality of data processors;

first means within said control means for initiating a query on behalf of a requesting data processor regarding the availability of requested data in said main memory;

second means within said control means for initiating a second query regarding the availability of a modified version of the requested data within any one of the aforesaid buffer memory units;

validation means within said buffer memory unit for indicating, in response to the second query, the one of the aforesaid buffer memory units containing the modified version of data;

third means within said control means for initiating a data retrieval from said main memory to the requesting data processor concurrent with the second query to each of the aforesaid buffer memory units;

means within said control means for detecting the state of said validation means;

means controlled by sAid detecting means for interrupting the initiated main memory data retrieval fetch function said initiating a main memory data store function when the state of said validation means indicates that one of the aforesaid buffer memory units contains the modified version of data; and

means operable concurrently with said interruption means for transmitting the modified version of data from the buffer memory unit so containing the modified version of data to the buffer memory unit of the requesting processor and simultaneously therewith to said main memory.

2. Initiating a read cycle of main memory for said requested data,

3. The apparatus of claim 1 wherein said data processors are a plurality of processors within a multi-processing computer system.

4. Detecting a modified version of data in one of said buffer memorys.

5. The apparatus of claim 4 wherein said second means initiates said query to buffer memory units consequent upon the unavailability of said requested data in a valid form in the buffer memory unit of said requesting data processor.

6. Writing said modified data into main memory.

7. The apparatus of claim 6 wherein said validation means further comprises a modified bit stored in a directory associated with each portion of said data in each of said buffer memories to indicate whether the data has been modified by said data processor.

8. The apparatus of claim 7 wherein said control means comprises a plurality of control units each connected to a data processor, the main memory and the other control units associated with other data processors.

9. The apparatus of claim 8 wherein said control unit associated with said requesting data processor operates simultaneously with the operation of the other control units when broadcasting its requesting data and initiates said data retrieval from main memory.

10. The apparatus of claim 9 wherein said control unit associated with said buffer memory, wherein a modified version of data was indicated, further contains means to control said conversion of said data retrieval to a data storage of said modified data into main memory and means to transmit said modified data to the requesting processor.

11. The apparatus of claim 10 further comprising means to query only the requesting data processor when a store operation is desired to main memory from said requesting data processor'"'"''"'"'s buffer memory.

12. The apparatus of claim 11 further comprising means within said control units to determine whether the requested data is located in its associated buffer memory.

13. A method of obtaining data in a data processing system which contains multiple users each with its own buffer memory unit comprising the steps of: