ADDRESSING AN INTEGRATED CIRCUIT READ-ONLY MEMORY

• US 3,771,145 A
• Filed: 02/01/1971
• Issued: 11/06/1973
• Est. Priority Date: 02/01/1971
• Status: Expired due to Term

• Current Assignee: Patricia P. Wiener
• Original Assignee: Patricia P. Wiener
• Inventors: Wiener, Patricia P.
• Primary Examiner(s): Konick, Bernard
• Assistant Examiner(s): Hecker, Stuart N.
• Application Number:
  US05/111,193
• Time in Patent Office: 1,009 Days
• Field of Search: 340/173R,173CA,173SP
• US Class Current: 365/240
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter

Abstract

A read-only memory of the MOS variety with address decoder, memory matrix and internal control for byte string extraction and sequencing. Beginning of a byte string is separately controlled, termination of extraction is redundantly established. Two chips can operate in phase opposition for doubling the overall byte string extraction rate from locations identified by a single address.

Claims

1. In an integrated circuit chip of the MOS variety, for use as read only memory, the combination comprising:

a plurality of runs in the chip provided as zones of particular conductivity, each run developed to establish a node, and isolated from each other;

circuit means on the chip connected to said runs of the plurality for charging the Respective nodes for a limited period of time;

at least one gate plating across the runs of the plurality, there being transistors of the FET variety developed in locations adjacent the gate plating where crossing a subplurality of the runs of the first plurality;

FET circuit means for applying a gating potential to the gate plating persisting beyond the period of time to obtain discharge of the sub-plurality of runs; and

FET circuit means responding to the change state of all the runs of the first plurality at a time succeeding said period.

2. In a circuit chip as in claim 1, including circuit means on the chip for charging all of the gate platings as nodes;

and address decoder means for discharging all but one of the gate plating nodes prior to termination of said period of time.

3. An integrated circuit memory comprising:

a first and a second memory matrix, each matrix having a plurality of addressing rows and extraction columns, rows and columns intersecting respectively in locations to the bit level, the plurality of locations of each matrix respectively arranged along rows and columns of the respective matrix, the locations of the plurality respectively storing data bits;

addressing means responsive to address codes and connected for concurrently addressing one row each of said first and second matrices;

byte extracting and columns selector means for alternatingly extracting bytes, plural bits in parallel being a byte, from the locations on the said addressed rows, through selection of columns of said columns;

clock means providing alternating clock signals and connected for alternatingly operating the said extracting and selector means to obtain the alternating extraction of bytes from the first and second matrices; and

merge means connected to merge the bytes extracted from the first matrix with the bytes extracted from the second matrix to obtain a string of bytes composed on the alternatingly extracted bytes.

4. A memory as in claim 3, and including second addressing means connected to receive a starting address for the sequence of extraction as provided by the selector means.

5. In a memory circuit on an integrated circuit chip having plural, individually addressable word locations, each word location holding a plurality of bytes, each byte having a plurality of bits, a read-out circuit comprising:

first means on the chip for defining a data matrix having addressing rows and data columns, the intersection of a row and of a column defining a memory location;

one byte for at least one word location defined by a particular combination of bits;

second means on the chip responsive to a first, externally applied addressing code and connected for addressing one of the rows, pursuant to such addressing the content of the memory locations is available on the columns;

third means on the chip and including shift register means for sequentially calling on the columns for one byte at a time and providing bit value defining signals representing one respective byte for external extraction of the bytes as provided in particular sequence;

fourth means on the chip connected to the third means for establishing a particular beginning of a byte call sequence; and

fifth means responsive to the particular bit combination when read and terminating the byte call sequence.

6. A memory as in claim 5, the fourth means including a decoder connected to be responsive to a second, externally applied byte addressing code permitting beginning of a byte call sequency with a byte ahead or behind of the particular byte, depending upon the byte addressing code as applied.

7. A memory, comprising:

a first chip and a second chip, each chip having addressing inputs interconnected externally to receive similar addressing signals;

each chip having output lines, interconnected externally to receive data from either chip;

a memory matrix on each chip having plural locations to the word level each connecteD to receive the addressing signals and to access one word location on each chip;

byte string extraction means on each chip operating to provide a byte sequence from the respectively accessed word location to the respective output lines;

clocking means on each chip for receiving a pair of interspaced clock pulse trains and providing the bytes in synchronism with one of the trains as received, followed by a pause in synchronism with the respective other train as received; and

means external to the chips for providing two clock pulse trains and connected for applying them in inverse order to the clocking means of the two chips.

8. A memory as in claim 7, each chip including means for receiving additional addressing signals and operating the respective byte string extraction from comparable places in each of the respectively accessed word locations on both chips;

and means on each chip to provide for independent but concurrent termination of byte string extraction.

9. In a memory circuit on an integrated circuit chip having plural, individually addressable word locations, each word location holding a plurality of bytes, each byte having a plurality of bits, a read-out circuit comprising:

first means on the chip for defining a data matrix having addressing rows and data columns, the intersection of a row and of a column defining a memory location;

second means on the chip responsive to a first, externally applied addressing code and connected for addressing one of the rows, pursuant to such addressing the content of the memory locations is available on the columns;

third means on the chip connected for sequentially calling on the columns for one byte at a time and providing bit value defining signals representing one respective byte for external extraction of the bytes as provided in particular sequence;

fourth means on the chip connected to the third means for establishing a particular beginning of a byte call sequence, and fifth means on the chip for establishing a particular end for the byte call sequence.

10. A memory as in claim 9, the fourth means including a decoder means connected to be responsive to a second externally applied byte addressing code, the third means including byte call counter, the fourth means presetting the counter to a state corresponding to the second code.

11. A memory as in claim 9, the fifth means including means responsive to a particular control byte when called to terminate the byte call sequence.

12. In a memory on an integrated circuit chip having a plurality of word locations, each word location holding a plurality of bytes, each byte having a plurality of bits, the combination comprising:

first means on the chip defining a data matrix that includes a plurality of columns of bit cells, each column of cells including a bit extraction column, one extraction column per bit position in a word location, the data matrix including a plurality of addressing rows, one row per word location and coupled to all columns of cells, one bit per column of cells;

second means on the chip defining a decoder network responsive to address bits applied externally to the chip, and having a plurality of outputs respectively coupled to the rows of the plurality, and including means to provide an addressing signal on one of the rows in response to a particular combination of applied address bits, so that the matrix applies the bits of the addressed location to the extraction columns and sustains the bits therein;

third means on the chip defining a counter progressing at a particular sequence thereby providing sequentially different enabling signals, while the data bits are sustained on said extraction columns;

fourth means connected to all of the extraction columns and to the third means and selecting the bits on some of the extraction columns in parallel and in response to one of the enabling signals from the counter, and providing a string of bytes in response to progression of thE counter and of the enabling signals as provided by the counter; and

fifth means for presenting the bits of a byte concurrently and the bytes as sequentially provided by operation of the fourth means, as a byte string for use external to the chip.

13. A memory as in claim 12, including another decoder on the chip responsive to a code representing a particular beginning of a byte string to be extracted from a word location, and coupled to the counter to preset the counter to a state from which to progress.

14. A memory as in claim 12, and including sixth means responsive to completion of byte string extraction for providing reset operation on the chip, the sixth means connected resetting the counter to a starting condition.

15. A memory as in claim 12, including another decoder on the chip coupled to the extraction columns as selected by the fourth means and responsive to a particular byte for terminating the readout from the addressed word location.

16. A memory as in claim 12, including means responsive to an externally applied code for presetting the counter to a particular state corresponding to a byte number within a word location as defined by the address bits as applied to the second means;

and means responsive to a particular bit combination in a byte on bit cell columns when selected by the fourth means, to terminate readout of the word location.

17. A memory as in claim 12, including means for preparing all word locations for readout, by addressing all rows, the second means eliminating the preparation for the nonaddressed row so that only the one row remains addressed.

18. A memory as in claim 12, and including a second chip similar to the integrated circuit chip and connected to receive the same address bits and having an output connected in parallel to the first means, the two chips including clocking means each for providing byte string extraction in response to two externally applied, alternating clock pulses, the two clocking means receiving alternating pulses in inverse order.

19. A memory as in claim 12, wherein the chip has field effect transistors of the insulated gate variety constituting the active elements, the data matrix having runs of zones of particular conductivity along the cells and constituting the extraction columns, the matrix rows constituting gate platings, under which transistors are or are not developed adjacent the several runs in selective representation of stored data.

20. A memory as in claim 19, wherein the extraction columns constitutes nodes, there being a plurality of additional runs of zones disposed so that each extraction column of the plurality is juxtaposed to an additional run, the bit cells transistors developed in between the respective extraction column and the juxtaposed additional run, the nodes being precharged by an externally applied signal, extraction columns being discharged into the respective additional run upon release of the external signal if there is a bit cell transistor of said transistor on such extraction column that is gated on by an addressing signal in the matrix row gate plating of such a transistor.

21. A memory as in claim 19, the extraction columns constituting nodes, the chip including means connected to be responsive to a first externally applied signal precharging all of the nodes, and means in association with each of the extraction columns and the transistors, if any, along the respective extraction columns to obtain selective discharge of extraction columns through bit cell transistors gated on by the gate plating of a matrix row.

22. A memory as in claim 21, each gate plating of a matrix row constituting a node, all of the latter nodes being charged in response to a second externally applied signal, the second means operating to discharge all but one of the latter nodes in response to address bits and upon release of the second signal, the first signal being released subsequently.

23. A memory as in claim 21, there being a partiCular plurality of columns of cells, equal in number to the number of bits in a byte having always a particular charge state upon release of the first signal, the columns of the particular plurality being called last by operation of the third and fourth means to provide a particular byte, and means responsive to the particular byte, to provide a termination signal.