METHOD AND APPARATUS FOR TESTING A DIGITAL LOGIC FET BY MONITORING CURRENTS THE DEVICE DEVELOPS IN RESPONSE TO INPUT SIGNALS

• US 3,772,595 A
• Filed: 03/19/1971
• Issued: 11/13/1973
• Est. Priority Date: 03/19/1971
• Status: Expired due to Term

• Current Assignee: John G. Turner, Nicholas D.E. Wolf
• Original Assignee: John G. Turner, Nicholas D.E. Wolf
• Inventors: De Wolf, Nicholas, Turner, John G.
• Primary Examiner(s): Corcoran, Robert J.
• Application Number:
  US05/126,035
• Time in Patent Office: 970 Days
• Field of Search: 324/73,158 71/11
• US Class Current: 714/736
• CPC Class Codes: G01R 31/2644 Adaptations of individual semiconductor devices to facilitate the testing thereof
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/31917 Stimuli generation or application of test patterns to the device under test [DUT]
• CPC Class Codes: G01R 31/3193 with comparison between actual response and known fault free response receiver details G01R31/31924

Abstract

A circuit tester examines MOS and other semiconductor logic devices at the high frequency of normal operation by measuring the current handling capability of the device. The tester performs the operation by sensing the current which the device delivers to, or draws from, a load of low resistance. The tester in one embodiment applies bursts of test data to the device under test at megaHertz rates by means of a pattern generator which allows ready adjustment of the burst length and configuration. The output detector for the tester senses the operation of the device under test as a source or sink of current.

Claims

1. Electrical test apparatus for the functional testing of a digital logic, integrated circuit, field-effect transistor device having plural logic terminals and normally responding to binary signals applied to a first set of said terminals to develop one of two impedance levels at each terminal of a second set thereof, said test apparatus comprising A. digital source means for applying a set of binary input signals in parallel to said first set of terminals, and for applying sets of such signals in succession at a first rate, B. output means 1. connected with terminals of said second set thereof, 2. presenting to each terminal of said second set an impedance having a resistive component with a maximum value at least one order of magnitude less than the larger of said impedance levels which the device under test normally develops at that terminal and with an RC time constant not greater than the reciprocal of said first rate, and 3. responding to the currents which the device under test develops at said terminals of said second set in response to each set of said input signals to produce further binary signals, and C. test output means connected with said source means and with said output means and producing a test output signal responsive to a comparison of the logic of said input signals with the logic of the signals said output means produces in response to said currents.

2. Electrical test apparatus as defined in claim 1 further characterized in that said resistive impedance component which said output means presents to each terminal of said second set has a maximum value at least two orders of magnitude less than the larger of said impedance levels which the device under test normally develops at that terminal.

3. Electrical test apparatus as defined in claim 1 further characterized in that said first rate at which said digital source means applies successive sets of said binary signals has a value of at least one megaHertz.

4. Electrical test apparatus for the functional testing of a digital logic, integrated circuit, field-effect transistor device having plural logic terminals and normally responding to binary signals applied to a first set of said terminals to develop binary signals at a second set of said terminals, said device normally developing one of two impedance levels at each terminal of said second set thereof in correspondence with the value of said binary signal it develops there, said test apparatus comprising A. digital source means for applying a set of binary input signals in parallel to said first set of terminals, and for applyiNg successive sets of such signals at a first rate, B. means forming a common return conductor in circuit between said device under test and said apparatus, C. a plurality of further terminals, each of which is associated with a different terminal of said second set thereof, D. a plurality of electrical conductor means, each of which is connected between a different terminal of said second set thereof and the associated further terminal, and each of which has a shunt capacitance to said return conductor with a magnitude less than the period corresponding to said rate divided by one-tenth of the larger of said impedance levels which the device under test normally develops at the terminal of said second set connected thereto, E. output means

5. Electrical test apparatus as defined in claim 4 further characterized in that A. said resistive impedance which said output means presents to each said further terminal has a maximum value at least two orders of magnitude less than the larger of said impedance levels which the device under test normally develops at the terminal of said second set which is connected to that further terminal, and B. in which each shunt capacitance between each said conductor means and said return conductor has a magnitude less than the period corresponding to said rate divided by one-one hundredth of the larger of said impedance levels which the device under test normally develops at the terminal of said second set connected to that conductor means.

6. Electrical test apparatus for the functional testing of an electronic digital logic, metal-oxide, field-effect transistor device having plural logic terminals and normally responding to binary-valued logic signals applied to a first set of said terminals to develop binary-valued signals at a second set of said terminals, said test apparatus comprising A. digital source means for producing plural sets of parallel binary input signals in succession and for applying them to said first terminals of the device under test, B. output means connected wtih the terminals of said second set thereof and responsive to the currents the device under test develops at said terminals of said second set in response to each set of said input signals, and C. test output means connected with said source means and with said output means and producing a test output signal responsive to a comparison of the binary logic of said input signals with the binary logic of the currents the device under test develops in response thereto at said terminals of said second set.

7. Test apparatus as defined in claim 6 in which said output means applies an impedance to each terminal in said second set thereof with a resistive component having a value at least one order of magnitude less than the maximum impedance the device under test normally develops at that second-set terminal thereof.

8. Test apparatus as defined in claim 6 in which said output means presents an impedance to each terminal in said second set thereof with a resistive component having a value at least one order of magnitude less than the maximum impedance which the device under test normally develops at that second-set terminal thereof, and in which said output means applies to each terminal in said second set thereof an electrical analog signal of selected voltage level and current value.

9. Test apparatus as defined in claim 6 A. in which said test output means has 1. plural resistive elements, each for connection in circuit with the current the device under test produces at a different terminal of said second set thereof, and each with a value at least two orders of magnitude less than the maximum impedance the device under test normally develops at that terminal, and

10. Test apparatus as defined in claim 6 in which said source means comprises A. plural register means, each having a number of successively-ordered binary digit-storage stages, B. commutator means associated with each register means and for applying the digit stored in each of a number of successively-ordered stages of said associated register to a terminal of said first set in successive cycles occurring at a first rate, and C. counting means for operating each commutator means for a selected number of cycles greater than the number of stages in the associated register means.

11. A method for testing electronic digital logic, integrated circuit, field-effect transistor devices having plural logic terminals and normally responding to binary signals applied to a first set of said terminals to develop binary signals at a second set of said terminals, said device normally developing one of two impedance levels at each terminal of said second set thereof in correspondence with the value of said binary signal it develops there, said method comprising the successive steps of A. applying successive sets of parallel binary input signals to said first set of terminals of the device under test at a first rate, B. sensing the magnitude of the current the device under test develops at each of said terminals of said second set thereof in response to each said set of input signals, C. producing a binary test signal in response to the current sensed at each said second-set terminal, D. comparing the logic of said input signals of each set thereof with the logic of said test signals resulting therefrom to produce a test output signal.

12. A method as defined in claim 11 in which said sensing step further includes A. presenting to each terminal of said second set thereof an impedance having a resistive component with a maximum value at least one order of magnitude less than the larger impedance level the device under test normally develops at that terminal, and B. sensing the magnitudes of the currents the device under test develops in said resistive impedance components.

13. A method as defined in claim 12 in which said sensing step further includes presenting each impedance with an RC time constant, computed with the resistance of said resistive component, not greater than the reciprocal of said first rate.

14. A method as defined in claim 11 in which said step of applying input signals further comprises, for each said first-set terminal, A. assembling a word of successively-ordered binary digits, B. applying each of a selected number of successively ordered bits of said word to that terminal in successive cycles, occurring at said first rate, and C. repeating said bit-applying step for a selected number of cycles greater than the number of digits in said word.