CLOCKED BOOTSTRAP INVERTER CIRCUIT

• US 3,774,055 A
• Filed: 01/24/1972
• Issued: 11/20/1973
• Est. Priority Date: 01/24/1972
• Status: Expired due to Term

• Current Assignee: Dilip C. Bapat
• Original Assignee: Dilip C. Bapat
• Inventors: Bapat, Dilip C.
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US05/220,092
• Time in Patent Office: 666 Days
• Field of Search: 307/205,251,279,208 328/176
• US Class Current: 326/97
• CPC Class Codes: H03K 19/01735 by bootstrapping, i.e. by positive feed-back
• CPC Class Codes: H03K 19/096 Synchronous circuits, i.e. using clock signals H03K19/01728, H03K19/01855 take precedence

Abstract

A clocked bootstrap inverter circuit including an inverting amplifier, an active load for the inverting amplifier including a capacitive bootstrapping circuit, a biasing circuit responsive to a first clocking signal and a second clocking signal 180* out of phase with the first clocking signal, and an amplifier disabling device responsive to a third clocking signal which is more than 180* out of phase with the first clocking signal. The biasing circuit alternately activates and inactivates the active load while the disabling device alternately disables the amplifier and provides a small time delay for allowing the bootstrapping circuit to be precharged.

Claims

1. A clocked bootstrap inverter circuit comprising a first source of potential;

a second source of potential;

an inverting amplifier having an output terminal, and being responsive to an input signal and operative to develop an output signal at said output terminal, said amplifier including a first FET having a first gate for receiving said input signal, a first source coupled to said first source of potential and a first drain coupled to said output terminal;

an active load means for said amplifier including a bootstrapping circuit, said load means having a conductive state and a nonconductive state, said load means including a second FET having a second gate, a second source coupled to aid output terminal and a second drain coupled to said second source of potential;

biasing means responsive to a first clocking signal and operative to render said load means alternately conductive and nonconductive, said biasing means including a third FET and a fourth FET, said third FET having a third gate for receiving said first clocking signal, a third source coupled to said second gate, and a third drain coupled to said second source of potential, said fourth FET having a fourth gate for receiving a second clocking signal which is 180* out of phase with said first clocking signal, a fourth source coupled to said first source of potential and a fourth drain coupled to said second gate; and

disabling means responsive to a third clocking signal and operative to periodically disable said amplifier, said disabling means including a fifth FET having a fifth gate for receiving said third clocking signal, a fifth source coupled to said first source of potential, and a fifth drain coupled to said output terminal, said third clocking signal being more than 180* out of phase with said first clocking signal.

2. A clocked bootstrap inverter circuit comprising a first source of potential;

a second source of potential;

an inverting amplifier having an output terminal, and being responsive to an input signal and operative to develop an output signal at said output terminal, said amplifier including a first FET having a first gate for receiving said input signal, a first source coupled to said first source of potential and a first drain coupled to said outut terminal;

an active load means for said amplifier including a boot-strapping circuit, said load means having a conductive state and a nonconductive state, said load means including a second FET having a second gate, a second source coupled to said output terminal and a second drain coupled to said second source of potential;

biasing means responsive to said first clocking signal and operative to render said load means alternately conductive and nonconductive, said biasing means including a third FET having a third gate coupled to said second source of potential, a third source coupled to said second gate, and a third drain for receiving said first clocking signal; and

disabling means responsive to a second clocking signal and operative to periodically disable said amplifier.

3. A clocked bootstrap inverter circuit as recited in claim 2 wherein said disabling means includes a fourth FET having a fourth gate for receiving said second clocking signal, a fourth source coupled to said first source of potential, and a fourth drain coupled to said output terminal, said second clocking signal being more than 180* out of phase with said first clocking signal.

4. A clocked bootstrap inverter circuit comprising a first source of potential;

a second source of potential;

an inverting amplifier having an output terminal, and being responsive to an input signal and operative to develop an output signal at said output terminal;

an active load means for said amplifier including a boot-strapping circuit, said load means having a conductive state and a nonconductive state;

said load means including a first FET having a first gate, a first source coupled to said output terminal, and a second drain coupled to said second source of potential;

biasing means responsive to a first clocking signal and operative to render said load means alternately conductive and nonconductive, said biasing means including, a second FET responsive to said first clocking signal and operative to couple said first gate to said second source of potential, and a third FET responsive to a second clocking signal and operative to couple said first gate to said first source of potential, said second clocking signal being 180* out of phase with said first clocking signal; and

disabling means responsive to a third clocking signal and operative to periodically disable said amplifier, said disabling means including a fourth FET responsive to said third clocking signal and operative to couple said output terminal to said first source of potential, said third clocking signal being more than 180* out of phase with said first clocking signal.

5. A clocked bootstrap inverter circuit comprising a first source of potential;

a second source of potential;

an inverting amplifier having an output terminal, and being responsive to an input signal and operative to develop an output signal at said output terminal;

an active load means for said amplifier including a bootstrapping circuit, said load means having a conductive state and a nonconductive state, said load means including a first FET having a first gate, a first source coupled to said output terminal, and a first drain coupled to said second source of potential;

biasing means responsive to a first clocking signal and operative to render said load means alternately conductive and nonconductive, said biasing means including a second FET having a second gate coupled to said second source of potential, a second source coupled to said first gate, and a third drain for receiving said first clocking signal;

disabling means responsive to a second clocking signal and operative to periodically disable said amplifier, said disabling means including a third FET responsive to said second clocking signal and operative to couple said output terminal to said first source of potential.