DIGITAL SECOND-ORDER PHASE-LOCKED LOOP

• US 3,777,272 A
• Filed: 09/18/1972
• Issued: 12/04/1973
• Est. Priority Date: 09/18/1972
• Status: Expired due to Term

• Current Assignee: Carl R. Tegnelia, Christopher Carl, Fletcher James C Administrator of The National Aeronautics and Space Administration With Respect To An Invention of, Jack K. Holmes, N/a,
• Original Assignee: Carl R. Tegnelia, Christopher Carl, Fletcher James C Administrator of The National Aeronautics and Space Administration With Respect To An Invention of, Jack K. Holmes, N/a,
• Inventors: Tegnelia, Carl R., Fletcher, James C. Administrator of the National Aeronautics and Space, N/a,, Carl, Christopher, Holmes, Jack K.
• Primary Examiner(s): Brody, Alfred L.
• Application Number:
  US05/290,030
• Time in Patent Office: 442 Days
• Field of Search: 329/50,104,122,126 328/118 325/320 178/66,88
• US Class Current: 327/156
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions

Abstract

A digital second-order phase-locked loop is disclosed in which a counter driven by a stable clock pulse source is used to generate a reference waveform of the same frequency as an incoming waveform, and to sample the incoming waveform at zero-crossover points of the reference waveform. The samples are converted to digital form and accumulated over M cycles, reversing the sign of every second sample. After every M cycles, the accumulated value of samples is hard limited to a value SGN + OR - 1 and multiplied by a value Delta 1 equal to a number n1 of fractions of a cycle. The SGN values are accumulated to form a value epsilon which is multiplied by a value Delta 2 equal to a number n2 of fractions of a cycle, where n1 is greater than n2. The product Delta 2 epsilon is added to the product Delta 1 SGN at the end of every M cycles to form an error signal in digital form. That error signal is used to advance or retard the counter according to the sign of the sum by an amount equal to the sum Delta 1 SGN + Delta 2 epsilon , this continually synchronizing the output waveform of the counter with the incoming waveform.

Claims

1. A digital second-order phase-locked loop connected to receive an incoming waveform signal and adapted to generate a phase synchronized reference wave-form, said incoming waveform having two zero-crossover points where it crosses over from a negative to a positive and back to a negative voltage level with respect to a reference during each cycle, comprised of a stable source of clock pulses, a counter connected to receive said clock pulses at an input thereof to generate at an output terminal said reference waveform at the same frequency as said incoming waveform, means responsive to said counter for sampling said incoming waveform at times during the generation of said reference waveform at effective zero-crossover points thereof which correspond to said transition points of said incoming signal, and which would coincide with said transition points if said reference waveform were precisely iN phase with said incoming waveform, means for converting the voltage levels of said samples from analog-to-digital form, means for periodically accumulating said voltage levels of said samples as converted into digital form to form a first sum, means for hard limiting said first sum to a predetermined quantity SGN in digital form, retaining the sign of the first sum, means for multiplying said signal SGN by a fixed multiplier equal to less than a number of clock pulses counted during one cycle of said reference waveform generated by said counter, where said multiplier is a whole integer, means for resetting said periodic accumulating means after a predetermined number of cycles of said reference waveform have been generated by said counting means, means responsive to said resetting means for continually accumulating said SGN signals by adding each SGN signal to previously accumulated sum epsilon of SGN signals each time said periodic accumulating means is reset, means for multiplying the accumulated sum epsilon of SGN signals by a fixed multiplier equal to less than said fixed number by which said signal SGN is multiplied, where said fixed multiplier is a whole integer, means responsive to said resetting means for adding the product of said signal SGN and its multiplier to the product of said accumulated sum epsilon and its multiplier to obtain a phase error value and sign in digital form, means for periodically advancing said counter by an amount equal to the value of said phase error when said phase error sign is positive, and for retarding said counter by an amount equal to the value of said phase error when said phase error sign is negative.

2. The combination of claim 1 wherein the period of said last named means is equal to the period of said accumulating means.

3. The combination of claim 2 wherein said period is set by said resetting means.

4. A phase-locked loop for synchronizing a reference waveform with an incoming waveform, where said reference waveform is of the same frequency as said incoming waveform, comprised of a stable source of clock pulses, a counter for counting said clock pulses to produce said reference waveform, means responsive to said counter for sampling said incoming waveform at the transition points of said reference waveform from one level to the other each half cycle, said sampling means including means for converting each sample into digital form with a sign, means for accumulating said samples over a period of M cycles of said reference waveform, said accumulating means including means for reversing the sign of every other sample accumulated, to produce a phase error indicator signal in digital form with a sign, means connected to said sample accumulating means for accumulating a digital signal representing a fixed whole integer according to the sign of said phase error indicator signal at the end of each period of M cycles, thereby integrating said phase error indicator signal, means connected to said phase error indicator integrating means for adding or subtracting to the accumulated sum of digital signals, at the end of each period of M cycles, a digital signal representing a fixed number greater than said fixed whole integer, said number being a whole integer, the operation of adding or subtracting being controlled by the sign of said phase error indicator signal, thus producing a composite first and second order phase error indicator signal in digital form, and means for updating said counter by an amount equal to said composite phase error indicator signal at the end of each period of M cycles by advancing or retarding said counter according to the sign of said composite phase error signal.

5. The combination of claim 4 wherein said fixed whole integer is equal to one.

6. The combination of claim 5 wherein said phase error indicator signal is equal to one.

7. The combination of claim 4, wherein said incoming waVeform is modulated by synchronizing bits which alternate between one and zero every M cycles of said incoming waveform, thereby shifting by 180* the phase of alternate groups of M cycles of said incoming waveform, wherein said sampling means is responsive to said counter for taking additional periodic samples during each reference waveform cycle, and means for transmitting to bit-sync demodulating means all samples for use in a bit-sync tracking loop, and said accumulating means accumulates said samples by arithmetically adding or subtracting each sample under the combined control of said reference waveform and a bit-sync signal as separate input signals through a two-input logic network the output of which is at a given level only when one or the other, but not both, of the input signals is at a predetermined level, thus accounting for bit-sync modulation in the accumulation of samples.

8. The combination of claim 7 wherein said bit-sync signal is derived by a counter for counting M cycles of said reference waveform generating counter during which 2M samples of said incoming waveform are taken, and said counter is updated by said bit-sync tracking loop.

9. The combination of claim 8 including means for gating said bit-sync signal off, whereby accounting for bit-sync modulation of said incoming waveform can be terminated.

10. The combination of claim 9 wherein said incoming waveform is modulated by data bits which may be ones and zeroes, thereby shifting the phase by 180* of a group of M cycles of said incoming waveform for a bit one relative to a bit zero, including means for transmitting to data demodulating means all samples of said input waveform, and wherein said sign of said phase error indicator signal is transmitted to said means for integrating said phase error and to said means for producing said composite first and second order phase error indicator signal as separate input signals through a two-input logic network the output of which is at a given level only when one or the other, but not both, of the input signals is at a predetermined level, and the second input to said logic network is a data signal from said data demodulating means.