ANALOG TO PULSE RATE CONVERTER

• US 3,778,794 A
• Filed: 09/18/1972
• Issued: 12/11/1973
• Est. Priority Date: 09/18/1972
• Status: Expired due to Term

• Current Assignee: ABB Power T&D Limited (ABB Limited)
• Original Assignee: Andras I. Szabo, Dan V. Tarli, William E. Zitelli
• Inventors: Szabo, Andras I., Zitelli, William E., Tarli, Dan V.
• Primary Examiner(s): Miller, Jr., Stanley D.
• Application Number:
  US05/290,052
• Time in Patent Office: 449 Days
• Field of Search: 307/229,233,261,264,271,295 328/127 340/174.1A,174.1G
• US Class Current: 360/32
• CPC Class Codes: G01R 21/133 by using digital technique
• CPC Class Codes: H03K 7/06 Frequency or rate modulation, i.e. PFM or PRM
• CPC Class Codes: H03M 1/60 with intermediate conversion to frequency of pulses

Abstract

An analog to pulse rate converter includes an integrator circuit in which the integrator capacitor is charged at a rate corresponding to the level of an input signal. A logic control circuit causes the capacitor to discharge at a fixed rate during a fixed portion of the clock period whenever the capacitor charges above a predetermined charge level. Output pulses occur during each discharge cycle. The average frequency of the output pulses indicates the level of the input signal.

Claims

1. An analog to pulse rate converter comprising:

an input for receiving a varying analog input signal;

an integrator circuit having a charging and discharging capacitor;

a charging circuit connected between said input and the integrator capacitor for applying a charging current at a linear rate proportional to the level of said input signal;

a discharge circuit connected to said capacitor, said discharge circuit including a source of constant discharge current and a solid-state switch having conductive and non-conductive states, said capacitor being normally charged by said charging current when said switch is in said non-conductive state being discharged by said discharge current when said solid state switch is in said non-conductive state;

a source of clock pulses for generating clock pulses having fixed portions of opposite levels defining first and second logic states;

a decision control logic circuit including first and second inputs, said first input being responsive to a predetermined charge level developed on said capacitor, said second input being responsive to said first clock logic state so as to produce a discharge control logic signal when said first clock logic state occurs after said capacitor is charged above said predetermined level;

a discharge command circuit connected to said solid state switch to operate the switch between the conductive and non-conductive states, the command circuit being responsive to said discharge control logic signal and said second clock logic state so as to render the switch conductive when a complete fixed portion of said second clock logic state occurs after said discharge control logic signal is received so as to discharge said capacitor during a discharge cycle equal to the duration of the fixed portion of said second clock logic state;

an output pulse means for generating output pulses of constant duration in response to each discharge cycle of said capacitor; and

a time base generator for indicating timing reference intervals corresponding to a predetermined number of said clock pulses whereby the average number of output pulses occurring during each timing interval corresponds to the level of said input signal.

2. The converter as claimed in claim 1 including a comparator connected between said integrator circuit and said first input of said decision control logic circuit, said comparator being responsive to the integrator circuit output voltage for generating a logic signal to said first input when the predetermined charge level of said capacitor is reached.

3. The converter as claimed in claim 2 wherein said decision control logic circuit includes a gating circuit means having two inputs connected to said first and second inputs and two outputs, the logic circuit further including a latch circuit having two inputs each connected to one of said outputs of said gating circuit means and having first and second latch circuit outputs wherein said first latch output produces said discharge control logic signal, and further wherein said output pulse means includes a gating circuit means having an output responsive to said second output of said latch circuit so as to enable said second clock logic state to be generated at the output to form said output pulses.

4. The converter as claimed in claim 2 including a common source of alternating current signals connected to said source of clock pulses and to said time base generator, wherein said time base generator develops timing pulses defining said timing reference intervals, and means responsive to said output pulses and said tIming pulses for indicating the average frequency of said output pulses.

5. The converter as claimed in claim 4 wherein said indicating means includes a magnetic recorder having a continuously moving magnetic tape for recording said timing pulses along one tape path and said output pulses along another tape path adjacent said one tape path.

6. The converter as claimed in claim 5 including a pulse counter means connected between said output pulse means and said recorder wherein the pulse counter means generates a pulse in response to a predetermined number of output pulses to accommodate the rate of said output pulses to the recording rate of said recorder.