LEVEL SENSITIVE LOGIC SYSTEM

• US 3,783,254 A
• Filed: 10/16/1972
• Issued: 01/01/1974
• Est. Priority Date: 10/16/1972
• Status: Expired due to Term

• Current Assignee: Edward Baxter Eichelberger
• Original Assignee: Edward Baxter Eichelberger
• Inventors: Eichelberger, Edward Baxter
• Primary Examiner(s): Morrison, Malcolm A.
• Assistant Examiner(s): Malzahn, David H.
• Application Number:
  US05/297,543
• Time in Patent Office: 442 Days
• Field of Search: 235/152,156 307/203
• US Class Current: 708/100
• CPC Class Codes: G01R 31/318541 Scan latches or cell details
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• CPC Class Codes: G06F 11/273 Tester hardware, i.e. output processing circuits G06F11/263 takes precedence
• CPC Class Codes: G06F 9/4484 Executing subprograms
• CPC Class Codes: H03K 3/037 Bistable circuits

Abstract

A generalized and modular logic system for all arithmetic/logical units of a digital computer. Each arithmetic/logical unit of a computer is partitioned into sections formed of combinational logic networks and storage circuitry. The storage circuitry is sequential in operation and employs clocked dc latches. Two or more synchronous, nonoverlapping, independent system clock trains are used to control the latches. A single-sided delay dependency is imparted to the system. The feedback connections from the respective latch circuitry are made through combinational logic to other latch circuitry that has a system clock other than the system clock acting on the initiating latch circuitry. With each latch, there is provided additional circuitry so that each latch acts as one position of a shift register having input/output and shift controls that are independent of the system clocks and the system inputs/outputs. All of the shift register latches are coupled together into a single shift register.

Claims

1. A system of logic for performing at least one predetermined logical function in a general purpose digital computer, comprising means for generating a set of system input signals, means for generating a plurality of clock signal trains having a predetermined duration between the occurrence of signals in successive trains, a plurality of logic partitions, each of said partitions comprising a combinational network coupled to accept said set of input signals and to provide at least a first set of combinational signals, and sequential circuit means coupled to receive said first set of signals from the network in its partition under control of a selected one of said clock signal trains to store indications of the combinational logic of its associated network and to provide a set of outputs for said indications, means coupling said output indications from the sequential circuit means of each partition as a set of inputs to the combinational network of every other partition controlled by a clock signal train differing from the clock signal train exercising control in providing the set of output indications, and combinational means for accepting the sets of output indications to provide a logic system response.

2. The system of logic of claim 1, wherein at least one of said combinational networks is formed of plural stages of logic having a propagation time less than the predetermined duration.

3. The system of logic of claim 2, wherein a plurality of non-overlapping and independent clock sources provide the plural trains with the clock signals in each train having a duration sufficient to accomplish the clocking of the respective first sets of combinational signals into their associated sequential circuit means.

4. The system of logic of claim 3, wherein the number of said clock signal trains is equivalent to the number of partitions and the sequential circuit means of each partition is responsive to a distinct one of said clock signal trains.

5. The system of logic of claim 4, wherein said combinational network of each partition further provides a second set of combinational signals and means are provided in each partition to render the sequential circuit means responsive only to the presence of the second set of signals in that partition and the clock signal train provided to said partition to store the first set of combinational signals of that partition.

6. The logic system of claim 1, wherein the sequential circuit means of each partition is a set of clocked dc latches equivalent in number to the number in the first set of combinational signals for that partition for accepting as an input respective ones of said first set of combinational signals.

7. The logic system of claim 6, wherein said latches are polarity hold latches.

8. The logic system of claim 6, wherein said latches are clocked set-reset latches.

9. The logic system of claim 6, wherein each of said latches includes first and second bistable storage circuits connected with the output of the first storage circuit as an input to the second storage circuit, means for coupling an input signal to said first circuit independently of said first set of signals and for coupling an output signal from said second circuit, and means coupled to the first and second circuits of each of said latches for controlling the storing of signals in said circuits, whereby each of said latches is a shift register latch.

10. The logic system of claim 9, wherein all of the shift register latches are coupled together sequentially into at least one shift register with the first circuit of the first latch in the sequence accepting the input and the last in the sequence providing the output and with the second circuit of the other latches connected to the first circuit of the latches following them.

11. A functional logic unit for use in a general purpose digital computer, comprising a plurality of networks at least one of which is a combinational logic network, at least one of said networks being responsive to a set of unit input signals with each network providing at least a first set of signals, means for generating a plurality of clock signal trains, plural sequential circuit means arranged in groups coupled to respective ones of said networks for receiving respective first sets of signals from said networks under control of predetermined ones of said clock signal trains to store indications of the signals from its associated network and to provide a set of outputs for said indications, means coupling said output indications from the respective groups of plural sequential circuit means as sets of inputs to all networks except a network coupled to a sequential circuit means controlled by the clock signal train exercising control in providing the set of output indications, and means for accepting the sets of output indications to provide a functional logic unit response.

12. ThE unit of claim 11, wherein the number of groups of sequential circuit means is equivalent to the number of clock signal trains and each group is controlled by a different one of said trains.

13. The unit of claim 12, wherein said trains are non-overlapping and a predetermined duration exists between the occurrence of signals in successive trains, said duration being greater than the longest propagation time through said networks.

14. The unit of claim 12, wherein the combinational network further provides a second set of combinational signals and means are provided with each group of sequential circuit means coupled to said combinational network to render the groups responsive only to the presence of respective second sets of signals and the clock signal train for that group, whereby the first sets of signals from the networks are stored in respective groups.

15. The unit of claim 11, wherein each of the plural sequential circuit means includes means for providing access to them independent of the clock signal train control and the access means of each of said sequential circuit means are coupled together for providing scan-in/scan-out of said functional logic unit.

16. The unit of claim 15, wherein each of the sequential circuit means comprises first and second bistable storage circuits with the first of said circuits coupled to a respective one of said networks and to a clock signal train and operative to provide one of said set of outputs and said second bistable circuit is coupled to the output of the associated first bistable network, and said access means comprises input means coupled to said first circuit, output means coupled to said second circuit and means for controlling the entry of data into the first circuit and the exit of said data from the second circuit independent of the clock signal train control.

17. The unit of claim 16, wherein the entry and exit control means are coupled to all of said sequential circuit means and said sequential circuit means coupled together in cascade with the output of each said second bistable circuit except the last coupled as an input to the next succeeding first bistable circuit, the first bistable circuit receiving an independent data input and the last second bistable circuit providing an independent data output, whereby said plural sequential circuit means are coupled together as a register for accomplishing said scan-in/scan-out of said functional logic unit.

18. A functional logic unit for use in a general purpose digital computer, comprising a plurality of latches arranged in groups, means for generating a plurality of clock signal trains coupled to respective groups of said latches for controlling the latches, plural networks at least one of which is responsive to a set of unit input signals with each such network providing a set of network signal indications, means coupling the sets of network signal indications to respective groups of latches such that the indications are latched in the respective groups under the control of the respective clock signal trains, means coupling the outputs of the respective groups of latches as sets of inputs to all networks except a network coupled to a latch group controlled by the same clock signal train, and means coupling the outputs of the latch groups for providing a logic unit output indication that is a function of said set of unit input signals and said indications in the respective groups of latches.

19. The unit of claim 18, wherein means are provided between at least one latch group and its associated network for gating indications from the associated network on the clock train for that latch group.

20. The unit of claim 18, wherein each of the latches is a shift register latch and wherein the unit further comprises means coupling all of said latches together as a shift register, means providing access to and from said unit independent of said unit input signals, clock trains and logic unit output, and means for controllIng said access to said unit, whereby scan-in/scan-out is accomplished.