SOLID STATE MOTOR CONTROLLER FOR DISCONNECTING A MOTOR FROM A POWER SOURCE WHEN A PREDETERMINED UNDERVOLTAGE CONDITION PERSISTS FOR A PREDETERMINED TIME

• US 3,784,846 A
• Filed: 04/24/1972
• Issued: 01/08/1974
• Est. Priority Date: 04/24/1972
• Status: Expired due to Term

• Current Assignee: Bernard Coleman, John B. Krick
• Original Assignee: Bernard Coleman, John B. Krick
• Inventors: Krick, John B., Coleman, Bernard
• Primary Examiner(s): Miller, Jr., Stanley D.
• Application Number:
  US05/246,610
• Time in Patent Office: 624 Days
• Field of Search: 307/235,293 317/31,36TD,33SC,141S
• US Class Current: 327/50
• CPC Class Codes: H02H 3/247 having timing means
• CPC Class Codes: H03K 17/30 Modifications for providing a predetermined threshold before switching shaping pulses by thresholding H03K5/08

Abstract

A combination solid state voltage sensing and timing relay employed for disconnecting equipment from a line source when the line voltage drops below a preset voltage for a preset time period. Whereas the pick up voltage of the voltage sensor is fixed at a first level, the drop out voltage is adjustable by means of a variable resistance element to be at a value lying within a range which is just slightly below the pick up voltage at the top of the range to a value which is significantly below the pick up voltage. The time delay interval is adjustable by way of a second variable resistance over a range of the order of from 0.5 to 10 seconds. The output of the undervoltage timer is a single pole normally open solid state switch for selectively connecting or disconnecting the line source from the load, depending upon the condition from the source and the length of time during which this condition persists.

Claims

1. A solid state timer for selectively coupling an a.c. power source to a load only when the power source achieves a predetermined pick-up voltage and for decoupling said source from said load when the level of said source drops below a predetermined drop-out voltage for a predetermined time period, said timer comprising:

first means coupled to said source for generating a regulated d.c. output;

tracking means coupled to said source for developing a d.c. voltage level representative of and sensitive to changes in the output level of said source;

a timing circuit including a capacitor;

a solid state switch coupled between said source and said load, said switch having a gate electrode for selectively controlling the conductive state of said switch;

a control circuit powered by said first means and having an input coupled to said tracking means and having an output, said output coupled to said timing circuit;

a gate circuit coupled between said timing capacitor and the gate electrode of said solid state switch for turning said solid state switch on when said gate circuit is turned off, said gate circuit being turned off when said capacitor discharges below a predetermined level;

said control circuit being turned on when the output of said tracking means reaches a predetermined level whereby said control circuit charges said capacitor;

said gate circuit being turned off when said capacitor is charged to a predetermined level;

a clamping circuit having an output coupled to the input of said control circuit for enabling said control circuit to be turned on only when the clamping circuit is not conducting;

second normally operable switch means connected between said source and the input of said clamping circuit, said second switch means having an open position for uncoupling said clamping circuit from said source and a closed position for coupling said source to said clamping circuit;

said clamping circuit being turned on when said switch means is in the closed position to disable said control circuit;

feedback means coupled between the said gate circuit output and the input of said clamping circuit for maintaining said clamping circuit in the non-conductive state when said solid state switch is turned on and for turning on said clamping circuit when said solid state switch is turned off to prevent operation of said control circuit until said second switch means is reclosed.

2. The solid state timer of claim 1 further comprising an adjustable potential divider circuit coupled between the output of said second means and the input of said control circuit for adjustably controlling the level of the portion of the output of said second means coupled to the input of said control circuit to adjustably control the pick-up voltage level.

3. The solid state timer of claim 1 wherein said timing circuit is further comprised of adjustable voltage divider means for coupling a portion of the output of said timing circuit to said second switch means to adjustably regulate the elapsed tiMe at which said second switch means is turned off as said capacitor is discharging.

4. The solid state timer of claim 1 further comprising means coupled between said second switch means and the input of said clamping circuit for coupling a half-wave rectified d.c. signal to the input of said clamping circuit to turn said clamping circuit off when said second switch means is in said closed position.

5. A solid state timer for selectively coupling an a.c. power source to a load only when the power source achieves a predetermined pick-up voltage and for decoupling said source from said load when the level of said source drops below a predetermined drop-out voltage for a predetermined time period, said timer comprising:

first means coupled to said source for generating a regulated d.c. output;

tracking means coupled to said source for developing a d.c. voltage level representative of and sensitive to changes in the output level of said source;

a timing circuit including a capacitor;

a solid state switch coupled between said source and said load, said switch having a gate electrode for selectively controlling the conductive state of said switch;

a control circuit powered by said first means and having an input coupled to said second means and having an output, said output coupled to said timing circuit;

a gate circuit coupled between said timing capacitor and the gate electrode of said solid state switch for turning said solid state switch on when said gate circuit is turned off, said gate circuit being turned off when said capacitor discharges below a predetermined level;

said control circuit being turned on when the output of said tracking means reaches a predetermined level whereby said control circuit charges said capacitor;

said gate circuit being turned off when said capacitor is charged to a predetermined level;

a clamping circuit having an output coupled to the input of said control circuit for enabling said control circuit to be turned on only when the clamping circuit is not conducting;

second normally operable switch means connected between said source and the input of said clamping circuit, said second switch means having an open position for uncoupling said clamping circuit from said source and a closed position for coupling said source to said clamping circuit;

said clamping circuit being turned on when said switch means is in the closed position to disable said control circuit;

feedback means coupled between the said gate circuit output and the input of said clamping circuit for maintaining said clamping circuit in the non-conductive state when said solid state switch is turned on and for turning on said clamping circuit when said solid state switch is turned off to prevent operation of said control circuit until said second switch means is reclosed;

said control circuit comprising;

a complementary Schmitt trigger circuit including complementary type transistors;

the base of one of said transistors being coupled to the output of said second means, the collector of the other one of said transistors being coupled to said timing circuit.

6. A solid state timer for selectively coupling an a.c. power source to a load only when the power source achieves a predetermined pick-up voltage and for decoupling said source from said load when the level of said source drops below a predetermined drop-out voltage for a predetermined time period, said timer comprising:

first means coupled to said source for generating a regulated d.c. output;

tracking means coupled to said source for developing a d.c. voltage level representative of and sensitive to changes in the output level of said source;

a timing circuit including a capacitor;

a solid state switch coupled between said source and said load, said switch having a gate electrode for selectively controlling the conductive state of said switch;

a control circuit powered by said first means and having an input coupled to said seCond means and having an output, said output coupled to said timing circuit;

a gate circuit coupled between said timing capacitor and the gate electrode of said solid state switch for turning said solid state switch on when said gate circuit is turned off, said gate circuit being turned off when said capacitor discharges below a predetermined level;

said control circuit being turned on when the output of said tracking means reaches a predetermined level whereby said control circuit charges said capacitor;

said gate circuit being turned off when said capacitor is charged to a predetermined level;

a clamping circuit having an output coupled to the input of said control circuit for enabling said control circuit to be turned on only when the clamping circuit is not conducting;

second normally operable switch means connected between said source and the input of said clamping circuit, said second switch means having an open position for uncoupling said clamping circuit from said source and a closed position for coupling said source to said clamping circuit;

said clamping circuit being turned on when said switch means is in the closed position to disable said control circuit;

feedback means coupled between the said gate, circuit output and the input of said clamping circuit for maintaining said clamping circuit in the non-conductive state when said solid state switch is turned on and for turning on said clamping circuit when said solid state swtich is turned off to prevent operation of said control circuit until said second switch means is reclosed;

said switch gate circuit being comprised of a Schmitt trigger circuit having first and second transistors;

impedance means coupled between said first means and the gate electrode of said solid state switch;

said first transistor being coupled to said timing circuit and being turned on when the charge across said capacitor reaches a predetermined level, said second transistor being coupled to said first transistor and being turned off when said first transistor is turned on to shunt current passing through said impedance means away from the gate electrode of said solid state switch to render said solid state switch non-conductive when the output of said timing circuit has fallen below a predetermined level.

7. The solid state timer of claim 2 further comprising resistance means coupled to said adjustable potential divider circuit and the input of said control circuit for maintaining said control circuit in the on state once said control circuit is turned on.