LOW PARASITIC MICROWAVE PACKAGE

• US 3,784,884 A
• Filed: 11/03/1972
• Issued: 01/08/1974
• Est. Priority Date: 11/03/1972
• Status: Expired due to Term

• Current Assignee: Demir S. Zoroglu
• Original Assignee: Demir S. Zoroglu
• Inventors: Zoroglu, Demir S.
• Primary Examiner(s): Heyman, John S.
• Assistant Examiner(s): Wojciechowicz, E.
• Application Number:
  US05/303,466
• Time in Patent Office: 431 Days
• Field of Search: 317/234,5.4
• US Class Current: 257/664
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01011 Sodium [Na]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/19107 off-chip wires
• CPC Class Codes: H01L 2924/30105 Capacitance
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A low parasitic microwave transistor package is provided with a pair of parallel rectangular bonding rails extending from the metal header. A first insulating body having a metal film thereon is positioned closely between the two rails and is attached to the header. A microwave transistor die may be attached to the metal film on the insulating body. A second insulating body having an aperture therein is attached to the metal base, the aperture accommodating the two bonding rails and the first insulating body positioned therebetween. The alumina disk has two metal bonding pads formed thereon. A very low inductance, low resistance connection from the emitter of a transistor to the metal base may be provided by means of a plurality of parallel stitch bonds from the emitter bonding pads on the transistor die to the bonding rails. Balanced feeding may be provided to the emitter, base and collector.

Claims

1. A low parasitic package comprising:

a metal header;

a first bonding rail extending directly from a surface of said metal header;

a first thermally conductive insulator attached to said metal header adjacent to said first bonding rail, said first insulator having a mEtal film on a major surface thereof, said first thermally conductive insulator having no openings therein;

a second insulator attached to said metal header adjacent to said first bonding rail, said second insulator having an opening therein exposing said surface, said first thermally conductive insulator and said first bonding rail being within said opening, said second insulator having first and second metal regions thereon; and

, first and second metal lead members connected, respectively, to said first and second metal regions and extending externally of the package.

2. The low parasitic package as recited in claim 1 further including a second bonding rail extending directly from said surface of said metal header within said opening and parallel to said first bonding rail and to said surface of said metal header, said first insulator being positioned between said first and second bonding rails.

3. The low parasitic package as recited in claim 2 wherein said first and second bonding rails are integral with said metal header.

4. The low parasitic package as recited in claim 1 wherein said first insulator is beryllia.

5. The low parasitic package as recited in claim 1 wherein said second insulator is alumina.

6. A low parasitic package for a semiconductor die comprising:

a metal header;

first and second bonding rails extending from a surface of said metal header;

a first metallized thermally conductive insulator attached to said metal header adjacent to said first bonding rail and having the semiconductor die attached to said first metallized insulator, said first metallized insulator being positioned between said first and second bonding rails;

a second metallized insulator attached to said metal header adjacent to said first bonding rail, said second metallized insulator having an opening therein exposing said surface, said first thermally conductive insulator in said first bonding rail being within said opening;

a first dipole wire bond lead connecting a first electrode of the semiconductor die to said first and second bonding rails and a first metal lead member formed on a first metallized region of said second metallized insulator;

a second wire bond lead connecting a first metallized region of said first metallized insulator to said first metal lead member;

a second metal lead member formed on a second metallized region of said second metallized insulator; and

, a third wire bond lead connecting a second electrode of said semiconductor die to said second metallized region.

7. The low parasitic package as recited in claim 6 wherein said first and second bonding rails are integral with said metal header.

8. The low parasitic package as recited in claim 6 wherein said first metallized insulator is beryllia.

9. The low parasitic package as recited in claim 6 wherein said second metallized insulator is alumina.

10. The low parasitic package as recited in claim 6 wherein the first electrode of the semiconductor die is its emitter and the second electrode thereof is its base.

11. The low parasitic package as recited in claim 6 including a plurality of stitch wire bonding leads connecting the first electrode of the semiconductor die to said first and second bonding rails for producing a balanced low inductance connection between the first electrode of the semiconductor die and said metal header.

12. The low parasitic package as recited in claim 6 further including a plurality of wire bonding leads connecting the metallized region of said first metallized insulator to the first metal lead member.

13. The low parasitic package as recited in claim 6 further including a plurality of wire bonding leads connecting the second electrode of the transistor to the second metal lead member.

14. A low parasitic microwave transistor package comprising:

a rectangular silver header;

first and second bonding rails extending from and integral with a surface of said silver header, said first and second bonding rails being parallel;

a rectangular beryllia insulator brazed to said silver header at said surface between said first and second bonding rails, the exposed major surface of said beryllia insulator being metallized, and having the microwave transistor attached thereto;

a rectangular alumina insulator having a rectangular aperture therein, said first and second bonding rails and said rectangular beryllia insulator being within said rectangular opening;

first and second metallized regions on a surface of said rectangular alumina insulator, on opposite sides of said aperture in said rectangular alum-na insulator;

first and second metal lead members formed, respectively, on said first and second metallized regions;

a plurality of parallel stitch wire bonding leads connected between the emitter electrode of the microwave transistor and said first and second bonding posts;

a plurality of parallel wire bonding leads connecting said first metal lead member to the base lead of the microwave transistor; and

a plurality of parallel wire bonding leads connecting the collector of said microwave transistor to said second metal lead member.