SEQUENTIAL ADDRESSING NETWORK TESTING SYSTEM

• US 3,784,910 A
• Filed: 07/13/1972
• Issued: 01/08/1974
• Est. Priority Date: 07/13/1972
• Status: Expired due to Term

• Current Assignee: Tage Peter Sylvan
• Original Assignee: Tage Peter Sylvan
• Inventors: Sylvan, Tage Peter
• Primary Examiner(s): Rolinec, Rudolph V.
• Assistant Examiner(s): Hille, Rolf
• Application Number:
  US05/271,268
• Time in Patent Office: 544 Days
• Field of Search: 324/73AT,73PC,73R,51
• US Class Current: 324/500
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/67 Testing the correctness of wire connections in electric apparatus or circuits

Abstract

The testing apparatus disclosed herein is adapted to test backplane wiring so as to determine if all desired connections exist and whether any undesired connections may be present. Such backplanes typically comprise a multiplicity of terminal points which may be interconnected in arbitrary manner to form a plurality of networks of connected points. The tester employs an addressable switching and memory unit for each terminal point. When addressed, each point is first connected to a first bus and, when the addressing is terminated, is thereafter connected to a second bus, this second connection being maintained under the control of the memory or latch associated with each switching unit. Prior to being addressed, each point is in effect isolated by the switching unit and allowed to float in potential. As the successive points in a given network are addressed, the system tests for continuity between the first and second buses to determine if the desired connections exist. After all terminal points which should be in the selected network have been latched into connection with the second bus, all remaining points are commonly switched into connection with the first bus. Testing for isolation at this time determines whether any undesired connections affecting the selected network are present.

Claims

1. Apparatus for testing matrix wiring which interconnects a plurality of sockets each having a substantial number of connection terminal points, said apparatus comprising:

a plurality of circuit boards each of which is adapted to mate with a respective one of said sockets;

on each board, a respective continuity test switching means for each terminal, each test continuity switching means having an initial state in which the respective terminal is isolated, a second state in which the respective terminal is connected to a first bus and a third state in which the respective terminal is connected to a second bus;

for each test switching means, a latch circuit which is set by a respective select signal and which operates, during application of the select signal, to place the respective switching means in its second state and which operates following termination of the respective select signal to hold said switching means in its third state;

for each terminal, a respective isolation test switch means, responsive to a gate signal applied to all isolation test switch means simultaneously, for connecting the respective terminal to said first bus on the condition that the respective latch circuit is not set;

means for coupling addressing signals to all of said boards;

means responsive to a first portion of said addressing signals for selecting which of said boards will be responsive to the remainder of said addressing signals; and

, on each board, decoding means responsive to the remainder of said addressing signals for generating a select signal corresponding to the address for selecting which of the test switching means on that board is to be operated, whereby each network in the wiring matrix can be tested by successively addressing the points comprising the desired network to determine the existence of the desired connection pattern and by then applying the gate signal to determine isolation of that network from all other terminal points.

2. Apparatus as set forth in claim 1 wherein each continuity test switching means includes a MOS field-effect transistor of one conductivity type connecting the respective terminal point to said first bus and a MOS field-effect transistor of the opposite conductivity type connecting the respective terminal point to said second type and wherein said isolation test switching means comprises a pair of MOS field-effect transistors of said one conductivity type connected in serIes to form a conduction path between the respective point and said first bus in parallel with the first said field-effect transistor, one of said pair being controlled by said latch to open said conduction path when said latch is set, the conductivity of the other being proportionally controlled by said gate signal.

3. Apparatus for testing backplane wiring which interconnects a plurality of sockets each having a substantial number of connection terminal points, said apparatus comprising:

a plurality of circuit boards each of which is adapted to mate with a respective one of said sockets;

on each board, a respective test switching means for each terminal, each test switching means having an initial state in which the respective terminal is isolated, a second state in which the respective terminal is connected to a first bus and a third state in which the respective terminal is connected to a second bus;

for each test switching means, a latch circuit which is set by a respective select signal and which operates, during application of the select signal, to place the respective switching means in its second state and which operates following termination of the respective select signal to hold said switching means in its third state, each of said latch means being resettable, by means of a reset signal applied commonly to all of said latch means, to return said test switching means to said initial state;

means for coupling addressing signals to all of said boards;

on each board, decoding means responsive to said addressing signals for generating a corresponding select signal for selecting which of the test switching means is to be enabled, whereby, following resetting, continuity in a network can be tested by sequentially selecting those network test switching means corresponding to the points properly belonging to the network while testing for continuity between said first bus and said second bus.

4. Apparatus for testing backplane wiring which interconnects a plurality of sockets each having a substantial number of connection terminal points, said apparatus comprising:

a series of circuit boards each of which is adapted to mate with a respective one of said sockets;

on each board, a respective continuity test switching means for each terminal, each continuity test switching means having an initial state in which the respective terminal is isolated, a second state in which the respective terminal is connected to a first bus and a third state in which the respective terminal is connected to a second bus;

for each test switching means, a latch circuit which is set by a respective select signal and which operates, during application of the select signal, to place the respective switching means in its second state and which operates following termination of the respective select signal to hold said switching means in its third state, each of said latch circuits being resettable, by means of a reset signal applied commonly to all of said latch means, to return the respective continuity test switching means to said initial state;

for each terminal, a respective isolation test switch means, responsive to a gate signal applied to all isolation test switch means simultaneously, for connecting the respective terminal to said first bus on the condition that the respective latch circuit is not set;

shift register addressing means having successive stages distributed among said boards for selectively enabling a preselected group of said test switching means on one of said boards;

connection means for coupling electrical levels from each board to the next in the series, said electrical levels including said first bus and said second bus, said gate signal and said reset signal, signals linking successive stages of said shift register addressing means, and further parallel addressing signals applied commonly to all said boards;

on each board, decoding means responsive to said parallel addressing signals for selecting which of tHe test switching means in a group on that board can be selected, whereby continuity in a desired network can be tested by sequentially addressing the switching units corresponding to he points properly in the network while testing for continuity between said buses and isolation of said network can be tested by applying said gate signal commonly to the isolation test switching means while testing for isolation between said supply buses.