DATA TERMINALS

• US 3,786,415 A
• Filed: 11/14/1972
• Issued: 01/15/1974
• Est. Priority Date: 11/17/1971
• Status: Expired due to Term

• Current Assignee: Brian Harry Phillips, Robert Gary Young
• Original Assignee: Brian Harry Phillips, Robert Gary Young
• Inventors: Young, Robert Gary, Phillips, Brian Harry
• Primary Examiner(s): Morrison, Malcolm A.
• Assistant Examiner(s): Dildine, Jr., R. Stephen
• Application Number:
  US05/306,314
• Time in Patent Office: 427 Days
• Field of Search: 178/69.5R,69.5G 340/146.1D
• US Class Current: 714/798
• CPC Class Codes: H04L 25/0262 Arrangements for detecting the data rate of an incoming signal
• CPC Class Codes: H04L 7/048 using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Abstract

A data terminal for a digital signalling system is arranged to receive incoming data transmitted in serial form and to divide the data into multi-digit signal units for supplying to a processor. Receipt of the data is controlled by a timing generator having a cycle of time slots equal to the number of digits in a signal unit. The validity of each signal unit is checked, using check bits forming part of each unit, and a check fail indication is passed to the processor if an invalid unit is detected. If the processor receives a succession of check fail indications, it initiates resynchronisation of the terminal, by resetting the timing generator. For this purpose, the terminal has a pattern recognition circuit for extracting an indication of synchronisation from the incoming data.

Claims

1. A data terminal for a digital signalling system employing multi-digit signal units transmitted in serial form, said terminal having receiver circuitry comprising:

a timing generator having a cycle of time slots equal to the number of digits in a signal unit;

means responsive to said timing generator for dividing incoming serial data into said signal units for supplying to utilisation means;

synchronisation indicating means for deriving an indication of synchronisation from said incoming data, and resynchronisation means responsive to a command signal from said utilisation means to reset said timing generator in synchronism with the incoming data in response to a said indication of synchronisation.

2. A data terminal according to claim 1 wherein said resynchronisation means comprises means for halting said timing generator in response to said command signal, and means for restarting said timing generator at a predetermined point of its cycle upon occurrence of a said indication of synchronisation.

3. A data terminal according to claim 1 wherein said resynchronisation means comprises means for resetting the timing generator, without halting it, to a predetermined point of its cycle on occurrence of the next said indication of synchronisation following a said command signal.

4. A data terminal according to claim 1 wherein said resynchronisation means comprises means for producing an indication, for read out by said utilisation means, of the amount by which the timing generator is out of synchronism with the incoming data.

5. A data terminal according to claim 1, for use in a data signalling system wherein each of said multi-digit signal units comprises a message portion and a check portion having a predetermined correlation with the message portion at least on transmission thereof, wherein said receiver circuitry further comprises checking means for checking the correlation between the check portion and the message portion of each signal unit, and means for storing an indication of the absence of such a correlation for read out by said utilisation means.

6. A data terminal according to claim 5 wherein said synchronisation indicating means comprises means for recognising a predetermined pattern of digits occurring in a said signal unit of the incoming data.

7. A data terminal according to claim 5 wherein said synchronisation indicating means comprises means for recognising successive sequences of digits in the incoming data having said predetermined correlation as between a messaGe portion and a check portion.

8. A data terminal according to claim 5 wherein said resynchronisation means comprises means responsive to said checking means, for automatically resetting the timing generator in the event of said checking means indicating the absence of said predetermined correlation during the cycle of the timing generator immediately following a reset.

9. A data terminal according to claim 1 wherein said means for dividing incoming serial data into signal units comprises:

a transfer register;

a serial-to-parallel converter for receiving said incoming data in serial form and for writing a signal unit into the transfer register, in parallel, at a predetermined point of the cycle of said timing generator;

means for reading the contents of said transfer register into said utilisation means in response to a read instruction from said utilisation means;

overflow detection means for detecting an overflow condition wherein data is being received by said serial-to-parallel converter faster than it is being read out of said transfer register; and

means for inhibiting the writing of a signal unit from said serial-to-parallel converter into said transfer register during occurrence of a said overflow condition.

10. A data terminal according to claim 1 having transmitter circuitry comprising:

a transfer register;

means for writing data from said utilisation means into said transfer register in response to a write instruction from the utilisation means;

a parallel-to-serial converter for reading a signal unit in parallel from the transfer register at a predetermined point in the cycle of a transmitter timing generator and for transmitting said signal unit in parallel form;

underflow detection means for detecting an underflow condition wherein data is being transmitted from said parallel-to-serial converter faster than it is being written into said transfer register; and

means for inhibiting the reading of a signal unit from said transfer register into said parallel-to-serial converter during occurrence of said underflow condition.

11. A data terminal according to claim 1 having transmitter circuitry including parity checking means for verifying correct transmission of data between said utilisation means and said transmitter circuitry, and means for injecting a predetermined error into a signal unit to be transmitted, in response to a parity fault detected by said parity checking means.

12. A data terminal according to claim 11 further including means responsive to an instruction from said utilisation means to cause an incorrect parity bit to be applied to said parity checking means, thereby resulting in injection of said predetermined error.