DATA PROCESSING SYSTEM INCLUDING A SMALL AUXILIARY PROCESSOR FOR OVERCOMING THE EFFECTS OF FAULTY HARDWARE

• US 3,786,430 A
• Filed: 11/15/1971
• Issued: 01/15/1974
• Est. Priority Date: 11/15/1971
• Status: Expired due to Term

• Current Assignee: Edwin Vogt, Guenter Knauft, Johann Hajdu, Petar Skuin
• Original Assignee: Edwin Vogt, Guenter Knauft, Johann Hajdu, Petar Skuin
• Inventors: Hajdu, Johann, Knauft, Guenter, Skuin, Petar, Vogt, Edwin
• Primary Examiner(s): Springborn, Harvey E.
• Application Number:
  US05/198,881
• Time in Patent Office: 792 Days
• Field of Search: 340/172.5
• US Class Current: 703/21
• CPC Class Codes: G06F 11/1405 at machine instruction level
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B

Abstract

An electronic data processing system comprising a relatively large main processor, a relatively small auxiliary processor, and a bus system linking both of said processors. The auxiliary processor is linked, via the bus system, to various portions of the main processor including data registers, error checking circuits, and function decoders. If one of the error checking circuits within the main processor detects a machine malfunction, the auxiliary processor will be able, via the bus system, to determine the portion of the main processor in which the malfunction occurred (by detecting which error check circuit detected the malfunction), and to determine the function which the main processor was attempting to perform when the malfunction occurred (by examining the output of the function decoder). The auxiliary processor will then, also via the bus system, address a data register which furnished input data to the failing portion of the main processor and extract the data therefrom; the auxiliary processor will manipulate the data (in accordance with the function defined by the function decoder in the main processor) to produce the result that would have been produced if the malfunction had not occurred (thereby, in effect, simulating the malfunctioning portion of the main processor); and, again via the bus system, the auxiliary processor will transmit the result to a data register within the main processor which accepts output data from said failing portion. The main processor will then be restarted to continue processing.

Claims

1. An electronic data processing system comprising:

a main processing system which includes registers, functional units for executing functions, and error check circuits for indicating the occurrence of errors within said system;

a function simulation processing system for simulating functions performed by said functional units;

a bus system linking both of said processing Systems;

said function simulation processing system comprising;

supervising means connected through said bus system to said check circuits for identifying, in the case of an error, the particular functional unit which produced said error;

means for storing source information received via said bus system from the registers in said main processing system which supply data to said particular functional unit, means for operating upon said source information to produce a correct result by simulating the function of the functional unit which produced said error, and means for transferring said correct result via said bus system to said main processing system.

2. The electronic data processing system of claim 1 wherein:

said supervising means comprises addressing means connected to said check circuits through an address bus within said bus system for identifying, in the case of an error, the check circuit which signalled the occurrence of said error.