SIGNAL MODE CONVERTER AND PROCESSOR

• US 3,789,199 A
• Filed: 05/01/1972
• Issued: 01/29/1974
• Est. Priority Date: 05/01/1972
• Status: Expired due to Term

• Current Assignee: Allan Joseph Kotwicki
• Original Assignee: Allan Joseph Kotwicki
• Inventors: Kotwicki, Allan Joseph
• Primary Examiner(s): Ruggiero, Joseph F.
• Application Number:
  US05/249,383
• Time in Patent Office: 638 Days
• Field of Search: 235/150.5,152 328/167,151 333/18,28,7T 444/1
• US Class Current: 708/3
• CPC Class Codes: H03H 17/02 Frequency selective networks digital computers for complex mathematical operations G06F17/10

Abstract

An analog signal comparator is coupled to provide its output to a data processor which has digital outputs coupled through a digital-to-analog converter to an input of the comparator, for periodically producing in the processor digital representations of samples of another analog signal that is also applied to the comparator. In each sampling period, additional data processing is carried out with respect to the digital representations; and an output circuit coupled to the converter output employs a filter circuit to select only the results of the last-mentioned processing. The additional processing is shown for digital filters featuring single and tandem sections.

Claims

1. In combination, means for comparing magnitudes of a first analog signal and a second analog signal and producing a result signal indicative of the relative magnitudes of such signals, means for processing signals in accordance with a predetermined program, said processing means having an input connection and having a plurality of output connections at which digital signal representations of the signal processing results are presented, said processing means comprising means for performing first and second digital operations in first and second parts of each of plural recurrent time intervals with respect to said first analog signal, said first and second parts being of unequal durations, means for coupling said result signal from an output of said comparing means to said input connection, means, connected to said processing means output connections, for converting a digital signal representation to a corresponding analog signal representation thereof, an output circuit, said output circuit including passive signal filter means having transmission characteristics selected for suppressing analog signal effects in one of said time interval parts of each interval as compared to analog signal effects in the other part, and means for coupling said analog signal representation simultaneously to said comparing means as said second analog signal and to said output circuit.

2. In combination, means for comparing magnitudes of a first analog signal and a second analog signal and producing a result signal indicative of the relative magnitudes of such signals, means for processing signals in accordance with a predetermined program, said processing means having an input connection and having a plurality of output connections at which digital signal representations of the signal processing results are presented, said processing means comprising a parallel cellular logic processor, means for coupling said result signal from an output of said comparing means to said input connection, means, connected to said processing means output connections, for converting a digital signal representation to a corresponding analog signal representation thereof, an output circuit, and means for coupling said analog signal representation simultaneously to said comparing means as said second analog signal and to said output circuit.

3. The combination in accordance with claim 2 in which said processor comprises means, responsive to said result signal and operative in an initial part of each of plural analog signal sampling periods, for performing a first computational function to form at said output connections a digital representation of the magnitude of a sample of said first analog signal, and for thereafter performing a second computational function on said digital representation of such sample to form at said output connections a predetermined modification of said digital signal representation.

4. The combination in accordance with claim 3 in which said output circuit comprises a passive low-pass filter having cutoff frequency selected so that signals in said initial part of the sampling period are substantially suppressed as compared to signals in the remainder of said sampling period during transmission through said output circuit.

5. The combination in accordance with claim 2 in which said processor comprises a plurality of computational cells of substantially identical format and each including a controllable input circuit and a controllable output circuit, said cells being arranged into a predetermined plurality of plural-cell groups, means for coupling said groups in a tandem sequence in which cell output circuits of each group, except the last in said sequence, are connected to cell input circuits, respectively, of the following cell in said sequence, means for connecting said processor input connection in multiple to cell input circuits of the first cell group in said sequence, meaNs for connecting the cell output circuits of the first cell group in said sequence as said processor output connections to said converting means, and means for interconnecting all of said cells in a global propagation sequence for controllably propagating signals from cell to cell.

6. In combination, an analog signal input circuit and an analog signal output circuit, means for comparing analog signal magnitudes and producing a two-valued output signal indicative of which compared signal is the larger, means for connecting said signal input circuit to supply a first analog signal to said comparing means, a parallel cellular logic processor comprising a programmed control unit and at least one group of processing cells all connected to receive the same control signals from said control unit, said processing cells having digital signal output circuits, means for connecting said comparing means output signal to all cells of said group, means, connected to receive signals from a group of said cell output circuits, for converting a plurality of digital input signals into a corresponding analog output signal, means for connecting said corresponding analog output signal to both said analog signal output circuit and an input of said comparing means, and means, in said control unit, for operating the last mentioned cell group in a program for periodically sampling said analog signal input circuit through said comparing means and computing a corresponding digital representation of an analog signal sample so obtained, said operating means further operating the same cells in a program, in each sampling period, for computing an least one predetermined modification of said sample for application to said digital signal output circuits.

7. The method of converting and digitally filtering an analog electrical input signal in a signal mode converting and digital filtering circuit, comprising the steps of 1 coupling to a first input of a comparator circuit the analog input signal, 2 sampling the comparator output signal at least at the Nyquist rate for the signal at inputs of a multi-cell, parallel cellular logic, digital processor circuit, 3 producing on plural outputs of said processor circuit an approximation of the analog input signal in the form of multi-bit binary signal, 4 converting the binary approximation signal into an analog representation in a digital-to-analog conversion circuit, 5 feeding back the analog representation of tbe binary approximation signal to a second input of said comparator circuit, 6 in said processor circuit correcting each bit of the binary approximation signal in accordance with the value of the comparator output signal until the corrected binary signal approximates the analog input signal to an accuracy corresponding to the value of the least significant bit in the binary signal, 7 digitally filtering the final version of the binary approximation signal in said processor, and 8 during substantially all of the sampling period in which the analog input signal is digitally filtered and subsequent to the final digital approximation thereof, producing on the plural outputs of said processor circuit the multi-bit digital result of the digital filtering that occurred during the prior sampling period.

8. The method of digitally filtering an analog electrical input signal in a signal mode converting and processing circuit, comprising the steps of 1 sampling the analog input signal at the input of said circuit, said sampling being repeated at least at the Nyquist rate for the signal, 2 converting the analog input signal in said circuit into a multibit digital approximation of the signal, 3 digitally filtering the digital approximation in said circuit during the same sampling period and following the conversion of the input signal, and 4 during substantially all of the last mentioned period and subsequent to the conversion portion thereof, producing as the output of Said circuit the result of the digital filtering of a prior sampling period.