MULTI-FREQUENCY SIGNAL GENERATOR

• US 3,792,360 A
• Filed: 08/14/1972
• Issued: 02/12/1974
• Est. Priority Date: 08/14/1972
• Status: Expired due to Term

• Current Assignee: Earl F. Carlow
• Original Assignee: Earl F. Carlow
• Inventors: Carlow, Earl F.
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US05/280,620
• Time in Patent Office: 547 Days
• Field of Search: 328/14,155,21,27,55,48
• US Class Current: 327/107
• CPC Class Codes: H04L 27/122 using digital generation of carrier signals digital function generators G06F1/02, H04L17/10; generating pulses having stepped portions using digital techniques H03K4/026

Abstract

The time taken to count up a binary counter is made adjustable by selectively phase-shifting a series of pulses passing into the counter and originating from a fixed frequency clock. The electronic pulses originating from the clock pass through a phase-shifting network, the shifting being responsive to and dependent upon digital data input in the form of electronic signals. A control circuit controls the phase-shifting network to produce a total counter cycle time that is representative of the digital data input. The output of the counter serves as an input to a sine wave synthesizer for providing an output sine wave of a frequency directly related to the state of the input digital data signal.

Claims

1. A multi-frequency signaling system having a source of periodic pulses, for receiving digital data in the form of electronic signals and digital waveform synthesizer output means for producing an analog signal output whose frequency is representative of the digital data input comprising:

a. a phase-shifting network, adapted to receive the periodic pulses, for selectively shifting the phase of the periodic pulses by one-half of one periodic pulse and for selectively delaying the phase of the periodic pulses by one periodic pulse;

b. binary counting means, adapted to receive the pulses from the phase-shifting network, having output means operatively connected to the digital waveform synthesiZer output means and to the phase-shifting network, and having further output means; and

c. control means, connected to the further output means, responsive to the count of the binary counting means, operatively connected to the phase-shifting network for selectively permitting the phase shifting means to operate at a prescribed count and for selectively causing the modulation means to operate at least at one selected count.

2. The system of claim 1 wherein the phase-shifting network further comprising:

a. i. one-half cycle phase-shifting means, adapted to receive the periodic pulses, for selectively shifting the phase of the periodic pulses by one-half of one periodic pulse; and

ii. pulse frequency modulation means, adapted to receive the pulses from the phase-shifting means, for selectively delaying the phase of the periodic pulses by one periodic pulse.

3. The system of claim 1 wherein the control means further comprise:

c. i. input means for receiving the digital data electronic signals; and

ii. frequency indicia means for receiving an electronic channel indicator, the control means being responsive to the indicator, in combination with the digital data electronic signals and at least one prescribed count of the binary counting means, for causing the pulse frequency modulation means to operate to extend the counting means cycle time.

4. The system of claim 3 wherein the binary counting means further comprise a binary counter having n flip-flop stages.

5. The system of claim 4 wherein the flip-flop of the least significant stage of the binary counter is operatively connected to respond to the frequency indicia means for selective bypassing to effectively change the counter to a binary counter having n-l stages.

6. The system of claim 4 wherein the pulse frequency modulation means further comprise at least one unit having:

enabling means, adapted to be conditioned by the control means;

delaying means, operatively connected to the enabling means, for delaying the periodic pulses by one periodic pulse when the enabling means are conditioned; and

bypass means, for directing the periodic pulses away from the delaying means and through the pulse frequency modulation means without delay when the enabling means are not conditioned.

7. The system of claim 5 wherein the pulse frequency modulation means further comprise a plurality of units, connected in series, for selective activation, each unit comprising:

enabling means, adapted to be conditioned by the control means;

delaying means, operatively connected to the enabling means, for delaying the periodic pulses by one periodic pulse when the enabling means are conditioned; and

bypass means, for directing the periodic pulses away from the delaying means and through the pulse frequency modulation means without delay when the enabling means are not conditioned.

8. The system of claim 7 wherein the enabling means further comprise a first and second latch circuit.

9. The system of claim 8 wherein the bypass means further comprise an output gate having an input from the one-half cycle phase-shifting means and an input from the output of the second latch circuit for disabling the output gate when the second latch circuit is conditioned.

10. The system of claim 9 wherein the delaying means further comprise a first gate, having an input from the one-half cycle phase-shifting means and an input from the first latch circuit for disabling the first gate when the latch circuit is conditioned, and a second gate having an input from the output of the first gate, responsive to the control circuit for disabling the second gate when the first gate is disabled.

11. The system of claim 10 wherein n 9 and the output of the stages are designated B1, B2, B3, B4, B5, B6, B7, B8 and B9, in succession, where B1 is the output of the least significant stage and B9 is the output of the most significant stage, each of the outputs serving as an input to the control means.

12. The system of claim 11 wherein the digital data electronic signal input is in the form of pulses wherein a 1 is designated D and a 0 is designated D, and the channel indicator is designated C when it is in the 1 state and designated C when it is in the 0 state, and wherein the pulse frequency modulation means is comprised of six units.

13. The system of claim 12 wherein the control means has one output connected to each of the six units, the outputs being designated P1, P2, P3, P4, P5 and P6, the control means being wired to establish the following respective logic configurations:

P1 B1.C + B3.C P2 B2.(C + D) + D5.(C + D) P3 B4.D + B9.D P4 B6.C.D P5 B7.D P6 B8.C.D

14. The system of claim 1 wherein the phase-shifting network further comprises:

a. iii. one-half cycle phase-shifting means, adapted to receive the periodic pulses, for selectively delaying the phase of the periodic pulses by one-half of one periodic pulse; and

iv. pulse frequency modulation means, adapted to receive the pulses from the phase-shifting means, for selectively delaying the phase of the periodic pulses by one periodic pulse.

15. A method of providing a sine wave whose frequency is indicative of the binary state of a digital input, comprising the steps of:

a. generating a series of periodic pulses;

b. selectively shifting the phase of the periodic pulses by one-half of one periodic pulse, responsive to the digital input;

c. selectively delaying the phase of the periodic pulses by one periodic pulse, responsive to the digital input;

d. causing a counter to count the selectively shifted and selectively delayed periodic pulses; and

e. synthesizing a sine wave output whose period is equal to the cycle time of the counter.

16. A method of providing a sine wave whose frequency is indicative of the binary state of a ditital input and of a channel designation, comprising the steps of:

a. generating a series of periodic pulses;

b. receiving the digital input;

c. receiving a voltage level indicative of a channel designation;

d. selectively delaying the phase of the periodic pulses by one-half of one periodic pulse;

e. selectively delaying the phase of the periodic pulses by one periodic pulse;

f. causing a counter of n stages to count the selectively shifted and selectively delayed periodic pulses;

g. combining selected ones of the output of the n stages with the digital data and the channel designation in logic fashion to cause the selective delaying by one-half of one periodic pulse and by one periodic pulse; and

h. synthesizing a sine wave output whose period is equal to the cycle of time of the counter.

17. The method of claim 16 wherein the step of synthesizing a sine wave output further comprises:

h. i. providing a plurality of weighted resistors;

ii. selectively causing a current to flow through each weighted resistor providing a voltage level at each resistor, the time of selection being dependent upon the binary contents of selected stages of the counter; and

iii. filtering the waveform formed by the voltages to provide a smoothed sine wave.