MULTI-COMPUTER VEHICLE CONTROL SYSTEM WITH SELF-VALIDATING FEATURES

• US 3,794,834 A
• Filed: 03/22/1972
• Issued: 02/26/1974
• Est. Priority Date: 03/22/1972
• Status: Expired due to Term

• Current Assignee: Sasib SpA (Is Company SRL)
• Original Assignee: Donald B. Marsh, Henry C. Sibley, John H. Auer Jr
• Inventors: Auer, John H. Jr., Marsh, Donald B., Sibley, Henry C.
• Primary Examiner(s): Forlenza, Gerald M.
• Assistant Examiner(s): Libman, George H.
• Application Number:
  US05/237,196
• Time in Patent Office: 706 Days
• Field of Search: 246/187B 340/146.1C
• US Class Current: 246/187.00B
• CPC Class Codes: B61L 27/04 Automatic systems, e.g. controlled by train; Change-over to manual control
• CPC Class Codes: B61L 3/125 using short-range radio transmission

Abstract

An automatic vehicle control system for controlling the operation of a vehicle from a set of parallel operating computers in a central control station. A data communication link transmits vehicle performance reports from the vehicle to the central control station and transmits vehicle command messages from the central control station to the vehicle. Validating circuitry in the vehicle validates received vehicle command messages by verifying the messages originated from both computers in the central control station. A portion of the vehicle command message included in the vehicle performance report is subsequently used by the two computers to validate the performance report message transmitted from the vehicle to the central control station.

Claims

1. An automatic vehicle control system for a vehicle controlled from a central control station, a data communication link between the vehicle and the central control station for transferring vehicle performance reports from the vehicle to the central control station and transferring vehicle command messages from the central control station to the vehicle, an on-line control system in the vehicle for decoding vehicle command messages and assembling performance report messages, a speed control unit acting in response to the vehicle command message decoded by the on-line vehicle control system for controlling acceleration and braking of the vehicle, a computer set in said central control station for computing the vehicle control data that is included in the vehicle command messages transmitted from the central control station to the vehicle, wherein the improvement comprises:

a data transfer buffer connecting to said computer set providing means for assembling the vehicle command messages for transfer to said vehicle;

a first and a second computer in said computer set providing means for calculating vehicle speed control data to be included in said vehicle command messages;

a compiling register in said data transfer buffer providing means for compiling said vehicle command message, said compiling register including a first register portion for storing data transferred from said first computer, a second register portion for storing data transferred from said second computer and a third register portion for storing data transferred from both said first and second computer and merged into said third portion.

2. The automatic vehicle control system of claim 1 wherein a validating field is included in said first register portion and said first computer provides programmed means for alternating data in said validating field in successively compiled vehicle command messages.

3. The automatic vehicle control system of claim 1 wherein:

a first validating field is included in said first register portion and said first computer provides programmed means for alternating data in said first validating field in successively compiled vehicle command messages, a second validating field is included in said second register portion and said second computer provides programmed means for alternating data in said second validating field in successively compiled vehicle command messages, and said first computer is coordinated with said second computer so that alternating data in said first register portion is complementary to alternating data of said second register portion.

4. The automatic vehicle control system of claim 3 wherein:

an identity word is formed in said compiling register, said identity word including the first validating field formed from said first register portion, the second validating field formed from said second register portion, and an address field formed from said third register portion, said on-line control system including an input register, an address recognition circuit operatively connected to said input register, and a validating circuit operatively connected to said address recognition circuit, said input register providing storage means for said identity word, said address recognition circuit providing means for testing said address field, said validating circuit providing means responsive to said address recognition circuit for validating the vehicle command message by testing the coordinated alternating of data in said first and said second validating fields.

5. The automatic vehicle control system of claim 4 wherein a first and second refresh circuit is included in said validating circuit, said first refresh circuit energized by said first validating field, said second refresh circuit energized by said second validating field, said first and second refresh circuits energized in a complementary manner corresponding to the alternating data in said first register portion being complementary to the alternating data in said second register portion.

6. The automatic vehicle control system of claim 5 wherein one of said first and second refresh circuits is deenergized by repetitive data occurring in said first register portion and said second register portion.

7. The automatic vehicle control system of claim 6 wherein said first and second refresh circuits are interconnected so that a first output signal is produced when both said first and second refresh circuits are energized, and a second output signal is produced when one of said first and second refresh circuits is deenergized.

8. The automatic vehicle control system of claim 1 wherein a logic gating circuit is interposed between said first and second computers and said compiling register for merging data transferred from said first and second computers into said third portion of said compiling register.

9. An automatic vehicle control system for a vehicle controlled from a central station, a data communication link between the vehicle and the central control station for transferring a vehicle performance reports from the vehicle to the central control station and transferring vehicle command messages from the central control station to the vehicle, an on-line control system in the vehicle for decoding vehicle command messages and assembling performance report messages, a speed control unit acting in response to the vehicle command messages decoded by the on-line vehicle control system for controlling acceleration and braking of the vehicle, a computer set in said central control station for computing the vehicle control data included in the vehicle command messages transmitted from the central control station to the vehicle, wherein the improvement comprises:

an identity word included in said vehicle commaNd message transmitted from the central control station to the vehicle, said identity word including a first and second validating field having alternating and complementary data supplied from said computer set, said on-line control system including an input register providing storage means for said identity word, and a validating circuit providing means for validating the vehicle command message by testing the complementary data in said first and second validating fields.

10. The automatic vehicle control system of claim 9 wherein a first and a second refresh circuit is included in said validating circuit, said first refresh circuit energized by said first validating field, said second refresh circuit energized by said second validating field, said first and second refresh circuits being energized in a complementary manner corresponding to alternating data in said first and second validating fields.

11. The automatic vehicle control system of claim 10 wherein a first signal path is maintained through said first refresh circuit when said first refresh circuit is energized by said first validating field, and said first signal path is maintained for 100 milliseconds following the each energization of said first refresh circuit.

12. The automatic vehicle control system of claim 11 wherein said first signal path becomes discontinuous within 250 milliseconds following an energization last applied to said first refresh circuit by said first validating field.

13. The automatic vehicle control system of claim 9 wherein:

a first and a second computer is included in said computer set, said first computer providing alternating signals for said first validating field and said second computer providing alternating signals for said second validating field in said identity word of successive vehicle command messages.

14. The automatic vehicle control system of claim 13 wherein:

said first and second computers are coordinated to provide complementary signals to said first and second validating fields respectively.

15. The automatic vehicle control system of claim 13 wherein:

a compiler register is includer in said central control station and provides means for compiling said vehicle command message, said compiling register including a first portion for storing data transferred from said first computer, a second portion for storing data transferred from said second computer, and a third portion for storing data merged from both said first and second computers.

16. The atuomatic vehicle control system of claim 15 wherein:

said first validating field is included in said first portion of said compiling register and said second validating field is included in said second portion of said compiling register.

17. The automatic vehicle control system of claim 15 wherein:

a logic gating circuit is interposed between said compiling register and said firat and second computers to merge data transferred from said first and second computers into said third portion of said compiling register.