METHOD OF PRODUCING SEMICONDUCTOR DEVICE

• US 3,795,976 A
• Filed: 10/16/1972
• Issued: 03/12/1974
• Est. Priority Date: 10/16/1972
• Status: Expired due to Term

• Current Assignee: Yasuhiko Ikeda
• Original Assignee: Yasuhiko Ikeda
• Inventors: Ikeda, Yasuhiko
• Primary Examiner(s): Lake, Roy
• Assistant Examiner(s): Tupman, W. C.
• Application Number:
  US05/297,870
• Time in Patent Office: 512 Days
• Field of Search: 29/580,583,588 204/192
• US Class Current: 438/460
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02183 the material containing tantalum, e.g. Ta2O5
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/31683 of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of producing a semiconductor device provided with a composite passivating film having excellent moisture resistance and a small surface charge density and a small leakage current, which comprises the steps of: contacting a semiconductor wafer heated to a temperature lower than about 700* C. in an atmosphere containing oxygen and a vapor of a volatile organic silicon compound capable of decomposing at a temperature lower than 700* C. in order to deposit silicon dioxide on a free surface of the wafer; forming a tantalum pentoxide film in an oxygen containing atmosphere on the silicon dioxide film by a reactive sputtering of tantalum; and subjecting the wafer to a heat treatment in a non-reducing atmosphere at a temperature of about 200* to about 400* C.

Claims

2. A method according to claim 1, wherein said non-reducing atmosphere contains oxygen, nitrogen, an inert gas, or mixtures thereof.

3. A method according to claim 2, wherein said inert gas is helium or argon.

4. A method according to claim 1, wherein said siliCon dioxide film is deposited to a thickness of less than about 1 Mu .

5. A method according to claim 4, wherein said silicon dioxide film is deposited to a thickness of between about 0.4 Mu to about 1 Mu .

6. A method according to claim 5, wherein said silicon dioxide film has a thickness of from about 0.4 Mu to about 0.95 Mu .

7. A method according to claim 1, wherein the sputtering of tantalum pentoxide is continued until the thickness of the tantalum pentoxide film is at least 0.2 Mu .

8. A method according to claim 1, wherein the sputtering of tantalum pentoxide is continued until the thickness of the tantalum pentoxide film is from about 0.2 Mu to about 0.7 Mu .

9. A method according to claim 1, wherein the silicon compound is monosilane, disilane or mixtures thereof.

10. A method according to claim 1, further comprising the step of forming a phosphorous glass layer consisting of a mixture of silicon dioxide and phosphorous pentoxide prior to the step of forming the tantalum pentoxide film, said tantalum pentoxide film being formed on said phosphorous glass layer.

11. A method according to claim 10, wherein said phosphorous glass layer is formed by depositing phosphorous pentoxide on said silicon oxide film.

12. A method according to claim 11, wherein said phosphorous pentoxide is deposited from an atmosphere containing PH3 or POCl3.

13. A method according to claim 10, wherein said phosphorous glass layer is formed by depositing a mixture of phosphorous pentoxide and silicon dioxide on said wafer from an atmosphere containing said silicon compound and PH3 or POCl3.

14. A method according to claim 1, wherein said silicon dioxide film is heat treated at a temperature of from about 700*C. to about 900*C. prior to the formation of the tantalum pentoxide film.

15. A method according to claim 10, wherein said phosphorous glass layer is heat treated at a temperature of from about 700*C. to about 900*C. prior to the formation of the tantalum pentoxide film.