RECIRCULATING BLOCK CIPHER CRYPTOGRAPHIC SYSTEM

• US 3,796,830 A
• Filed: 11/02/1971
• Issued: 03/12/1974
• Est. Priority Date: 11/02/1971
• Status: Expired due to Term

• Current Assignee: John Lynn Smith
• Original Assignee: John Lynn Smith
• Inventors: Smith, John Lynn
• Primary Examiner(s): Hubler, Malcolm F.
• Application Number:
  US05/194,836
• Time in Patent Office: 861 Days
• Field of Search: 178/22
• US Class Current: 380/37
• CPC Class Codes: H04L 2209/125 Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
• CPC Class Codes: H04L 2209/24 Key scheduling, i.e. generating round keys or sub-keys for block encryption
• CPC Class Codes: H04L 9/0618 Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation

Abstract

This is a cryptographic system for enciphering a block of binary data under the control of a subscriber cipher key consisting of a preassigned combination of binary symbols. The block of data is processed on a segmented basis with each segment of data being serially transformed in accordance with control signals determined from the binary values of key segments. The system is utilized within a data processing environment to provide complete privacy of data that is stored, or transmitted within a computer network. The ciphered message is developed by passing the clear message through a series of nonlinear transformations, each transformation being a function of the binary values that appear in the subscriber key.

Claims

1. A cryptographic system for enciphering or deciphering a block message consisting of, n, binary digits, under the control of a block cipher key consisting of, k, binary digits, the constituent digits of said message being grouped into segments having, p, binary digits, said system comprising:

means for loading a first group of message segments into a first store means and a second group of message segments into a second store means;

said first and second store means being formed from a plurality of storage cells;

means connected to the output of said first store means for generating a plurality of transformed signals, T, that are a function of said first group of message segments and selected binary digits of said cipher key;

a plurality of logic means interposed between the storage cells of said second store means for combining signals of said second message segments with said transformed signals, T, by a reversible mathematical operation;

said logic means being made selectively operative by the binary values of selected key digits, K, which in combination with a control signal gate the, T, signals to said plurality of logic means.

2. The system as defined in claim 1 wherein said means for generating transformed signals, T, comprises:

nonlinear transformation means for effecting a keyed substitution of said first group of message segments.

3. The system as defined in claim 2 further comprising:

third store means for maintainig said cipher key and presenting selected key digits on a plurality of, K, output lines;

selection means for causing said third store means to present identified key segments on said, K, output lines in accordance with a key digit accessing schedule.

4. The system as defined in claim 3 further comprising adder means for performing a modulo addition on information contained in said first and third store means and providing the sum, Sigma , to said nonlinear transformation means

5. The system as defined in claim 4 further comprising interchange means for interchanging the contents of said first and second store means.

6. The system as defined in claim 5 wherein each of said logic means comprises an exclusive-or gate for performing a modulo-2 addition of said, T, signals and the binary signal values contained in the store cells connected to said exclusive-or gate.

7. The system as defined in claim 6 wherein said second store means comprises:

a plurality of recirculating shift registers, each register having associated therewith a set of logic means interposed between storage cells within the register;

said logic means being selectively made operative by the binary values of selected digits of said cipher key so that at least one of said exclusive-or gates in each of said sets of logic means is operative when said shift registers are caused to shift their contents.

8. The system as defined in claim 7 further comprising counter means for counting the number of shift cycles performed by said recirculating shift registers so to enable the determination of when said interchange means is to be made operative and for enabling determination as to when said cryptographic system has completed an encipher or decipher operation.

9. An automatic process for enciphering or deciphering a block message consisting of, n, binary digits, under the control of a block cipher key consisting of, k, binary digits, said binary message digits being grouped into, p, digit segments, said process comprising the steps of:

loading a first group of message segments into a first storage location and a second group of message segments into a second storage location;

generating a plurality of transformed signals, T, as a nonlinear function of said first Group of message segments and the binary values of selected digits of said cipher key;

permuting said, T, signals as a function of the binary value of selected digits of said cipher key, K,;

combining the permuted, T, signals with a control signal for selectively controlling a reversible mathematical operation performed on message segments contained in said second storage location;

interchanging the contents of said first storage location with the contents of said second storage location;

repeating the above steps for a specified number of rounds;

whereby the final transformed message that appears in said first and second storage locations is a complex function of key and message binary signal values.