SYSTEM CLOCK FOR ELECTRONIC COMMUNICATION SYSTEMS

• US 3,803,568 A
• Filed: 04/06/1973
• Issued: 04/09/1974
• Est. Priority Date: 04/06/1973
• Status: Expired due to Term

• Current Assignee: AG Communication Systems Corp. (Nokia Corporation)
• Original Assignee: Carlos S. Higashide
• Inventors: Higashide, Carlos S.
• Primary Examiner(s): Caldwell, John W.
• Assistant Examiner(s): Lange, R.
• Application Number:
  US05/348,807
• Time in Patent Office: 368 Days
• Field of Search: 340/213R,333,248P,253P,146.1BE 307/64,65,71,219,204,216 328/128 333/3 325/2 235/153AE
• US Class Current: 714/814
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 11/1604 where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 11/2215 to test error correction or detection circuits
• CPC Class Codes: H04Q 3/54558 Redundancy, stand-by

Abstract

The system clock of the present invention is designed in such a manner that it is '"'"''"'"''"'"''"'"'fail-safe,'"'"''"'"''"'"''"'"' and a single failure of any kind will not prevent generation of clock pulses. More particularly, the system clock consists of two identical clock cards wired for redundant operation. One clock card functions as the main system clock (MSC), and the other functions as the standby system clock (SSC). Clock pulses normally are provided by the MSC to the appropriate subsystem timing generators, however, if a fault develops in the MSC, the pulse output of the MSC is inhibited and the function of providing pulses is transferred to the SSC. The transfer feature always takes place when an ALARM lead on the MSC goes to a logic one.

Claims

1. A clock system for providing clock pulses comprising a master system clock and a standby system clock, said clock pulses normally being provided by said master system clock and the output thereof being inhibited and the function of providing clock pulses being automatically transferred to said standby system clock when a fault develops in said master system clock, said transfer automatically taking place when alarm signal is placed on an alarm lead on said master system clock, said master system clock and said standby system clock each comprising output gate means, a pulse source for providing clock pulses to said output gate means, a source monitor for monitoring the output of said pulse source, said source monitor upon detecting that said pulse source fails to produce said output clock pulses causing an alarm signal to be placed on said alarm lead, said alarm signal indicating the failure of said pulse source and blocking said output gate means to prevent any pulses from leaving said system clock, an inhibit circuit coupled to and operable to control the passing of said clock pulses through said output gate means, said inhibit circuit normally permitting said clock pulses to pass through said output gate means and being operable to block said output gate means to prevent said clock pulses from leaving said system clock, an inhibit monitor for monitoring the operation of said inhibit circuit, said inhibit monitor causing said alarm signal to be placed on said alarm lead when a fault condition occurs within said inhibit circuit which causes the latter to inadvertently block said output gate means, said alarm lead of said master system clock being coupled to said inhibit circuit of said standby system clock and normally having a signal thereon to operate said inhibit circuit to block said output gate means of said standby system clock, said alarm signal when placed on said alarm lead of said master system clock operating said inhibit circuit of said standby system clock to permit said clock pulse to pass through said output gate means thereof, whereby said clock system is '"'"''"'"''"'"''"'"'fail-safe'"'"''"'"''"'"''"'"' and a single failure of any kind will not prevent generation of clock pulses.

2. The clock system of claim 1, wherein said master system clock and said standby systeM clock each further include alarm gate means, said source monitor and said inhibit monitor both being coupled to said alarm gate means and operable upon detecting a failure of one or both said pulse source and said inhibit circuit to cause said alarm gate to couple said alarm signal onto said alarm lead.

3. The clock system of claim 2, wherein said inhibit circuits each comprises a pair of flip-flop means, each having a pair of outputs, one of said outputs of each of said flip-flop means being coupled to and controlling said output gate means.

4. The clock system of claim 3, wherein said inhibit monitors each checks for a difference in the output states between said pair of flip-flop means and causes said alarm signal to be provided when a difference exists.

5. The clock system of claim 4, wherein said inhibit monitors each further includes means for causing said alarm signal to be provided when a difference exists for a pre-established time period.

6. The clock system of claim 2, wherein said inhibit circuits each comprises a pair of flip-flop means, each having a pair of outputs, one of said outputs of each of said flip-flop means being coupled to and controlling said output gate means, said inhibit monitors each including a pair of input gates and an output gate, one of said outputs of each of said flip-flop means being coupled to one of said pair of input gates and the other one of said outputs of each of said flip-flop means being coupled to the other one of said pair of input gates, said pair of input gates both being coupled to said output gate, said pair of input gates and said output gate being operable to detect the difference between the outputs of said pair of flip-flop means and to cause said alarm signal to be provided when a difference exists.

7. The clock system of claim 6, wherein said inhibit monitors each comprises means for causing said alarm signal to be provided when a difference exists for a pre-established time period.

8. The clock system of claim 2, wherein said source monitors each is comprised of flip-flop means having a pair of inputs and a pair of outputs, said flip-flop means when the same pre-established logic signal is coupled to each of said inputs being caused to toggle when said clock pulses are coupled to it to alternately couple said input logic signals to said pair of outputs, and gating means coupled to said outputs for causing said alarm gate to couple said alarm signal onto said alarm lead when said clock pulses do not appear.

9. The clock system of claim 8, wherein said source monitors each further comprise delay means, wherein said alarm signal is provided when said clock pulses disappear for a pre-established time period.

10. The clock system of claim 2, wherein said output gate means in each said master system clock and said standby system clock comprises a pair of output gates, said clock pulses passing through both of said output gates and thereby providing two clock pulse trains.

11. The clock system of claim 2, wherein said master system clock and said standby system clock each further having routining leads to which appropriate logic signals can be coupled to to simulate a fault condition in said inhibit circuit and in said source monitor, whereby said master system clock and said standby system clock can be routined for latent failures.

12. The clock system of claim 2, wherein said master system clock and said standby system clock each further comprise manually operable switch means for coupling appropriate logic signals to said inhibit circuit and said source monitor to simulate a fault condition therein, whereby said master system clock and said standby clock can be manually routined for latent failures.