CAPACITIVE-DISCHARGE TIMING CIRCUIT USING COMPARATOR TRANSISTOR BASE CURRENT TO DETERMINE DISCHARGE RATE

• US 3,808,466 A
• Filed: 06/05/1972
• Issued: 04/30/1974
• Est. Priority Date: 06/05/1972
• Status: Expired due to Term

• Current Assignee: Leonard Richard Campbell
• Original Assignee: Leonard Richard Campbell
• Inventors: Campbell, Leonard Richard
• Primary Examiner(s): Miller, Jr., Stanley D.
• Application Number:
  US05/259,711
• Time in Patent Office: 694 Days
• Field of Search: 307/235,293,246 330/3D 328/146-149
• US Class Current: 327/280
• CPC Class Codes: H03K 17/28 Modifications for introducing a time delay before switching modifications to provide a choice of time-intervals for executing more than one switching action H03K17/296
• CPC Class Codes: H03K 3/023 by the use of differential amplifiers or comparators, with internal or external positive feedback

Abstract

A timing capacitor is connected to one of the input terminals of a differential, transistor amplifier which forms part of an operational amplifier. The capacitor is controllably discharged through the base-to-emitter path of one of the differential transistors. An output signal of programmable duration is thereby derived from the operational amplifier according to the discharge duration of the capacitor.

Claims

1. An electronic timing circuit for providing an output signal of programmable duration comprising:

an operational amplifier characterized by a pair of inputer terminals connected to the base electrodes of a pair of transistors connected in an emitter-coupled differential amplifier circuit;

means for applying a reference potential to one of said input terminals;

energy storage means connected in circuit with the other of said input terminals;

means for charging said energy storage means to a predetermined level of potential in excess of said reference potential;

means for discharging said energy storage means primarily through the base-emitter path of the respective transistor connected to said other input terminal;

means for selecting the value of the combined emitter Currents of said pair of transistors thereby to provide means for adjusting the discharge rate of said storage means through said respective transistor connected to said other input terminal; and

means for deriving an output signal from said operational amplifier whereby the output state of said operational amplifier is determined by the potential difference between said input terminals, the discharge duration of said energy storage means determining the duration of said output signal from said operational amplifier.

2. An electronic timing circuit as defined in claim 1 further comprising a current mirror connected in common with said differential pair, the bias input for establishing the current flow through said current mirror providing the means for varying the discharge rate of said energy storage means.

3. In combination;

a pair of transistors connected in differential configuration;

first and second input terminals connected in circuit with the base electrodes of said transistor pair;

a programmable direct current source connected in circuit with the commonly connected emitter electrodes of said differential pair;

bias means for adjustably programming the current flow through said direct current source;

means for deriving an output signal from said transistors when the potential at a given one of said input terminals exceeds the potential at the other of said input terminals, means for deriving a reference potential for application to one of said input terminals;

energy storage means connected in circuit with the other of said input terminals;

means for charging said energy storage means to a predetermined level of potential; and

means for discharging said energy storage means primarily through said programmable direct current source via the transistor path connected in circuit with said other input terminal;

the discharge duration of said energy storage means varying substantially in direct proportion with the beta of said discharge transistor providing said discharge path and in inverse proportion to said current flow through said programmable direct current source, the duration of said output signal from said differential circuit means being determined by said discharge duration.

4. The invention as defined in claim 3 further comprising:

a semiconductor switching device having first and second main current carrying electrodes and a control electrode;

means for connecting said main current carrying electrodes in circuit with a load; and

means for applying the output signal from said differential circuit means to said control electrode.

5. An electronic timing circuit for providing an output signal of programmable duration comprising:

first and second transistors commonly connected in differential configuration;

first and second input terminals connected in circuit with the base electrodes of said transistors;

first and second load circuits connected in circuit with said first and second transistors;

a first current mirror connected in circuit with the commonly connected electrodes of said differential pair, the current drawn by said current mirror being equal to the total load current flowing through said first and second transistors;

means for deriving an output signal equal to the difference in load current flowing through said first and second transistors when the potential at a given one of said input terminals exceeds the potential at the other of said input terminals;

means for adjustably programming the current flow through said first current mirror;

means for deriving a reference potential for application to one of said input terminals;

energy storage means connected in circuit with the other of said input terminals;

means for charging said energy storage means to a predetermined level of potential in excess of said reference potential; and

means for discharging said energy storage means primarily through the transistor connecTed in circuit with said other input terminal.

6. The invention as defined in claim 5 wherein said first and second transistors have commonly connected emitter electrodes and said load circuits are connected in circuit with the collector electrodes thereof, said energy storage means discharging through the base-to-emitter path of said discharge transistor, the discharge duration of said energy storage means varying in direct proportion with the beta of said discharge transistor.

7. The invention as defined in claim 6 wherein means for deriving an output signal equal to the difference in load current flowing through said first and second transistors when the potential at a given one of said input terminals exceeds the potential at the other of said input terminals comprises:

a second and a third current mirror amplifiers having input circuits respectively furnishing said first and said second load circuits and having output circuits, and a fourth current mirror amplifier having an input and an output circuits connected to separate ones of said output circuits of said second and said third current mirror amplifiers, and providing at its said output circuit said output signal.

8. The invention as defined in claim 7 further comprising:

a semiconductor switching device having first and second main current carrying electrodes and a control electrode;

means for connecting said main current carrying electrodes in circuit with a load; and

means for applying said output signal to said control electrode.

9. An adjustable timing circuit comprising, in combination:

a source of operating and reference potentials and of a potential intermediate therebetween;

an operational amplifier which includes first and second transistors each having a base and an emitter and a collector electrodes, means coupling said first transistor base electrode to said intermediate potential, a current source having a first terminal connected to each of the emitter electrodes of said first and said second transistors and having a second terminal connected to said reference potential, means coupling the collector electrodes of each of said first and said second transistors to said operating potential, and a load across which an output signal is to be developed included in the coupling of at least one of the collector electrodes of said first and said second transistors to said operating potential;

charge storage means connected between the base electrode of said second transistor and said reference potential;

means for charging said storage means to a voltage level higher than said intermediate potential; and

means for adjusting the time required for said storage means to discharge primarily through the base-emitter path of said second transistor to a potential equal to said intermediate potential, which adjustment means comprises means for adjusting the level of current provided by said current source.

10. An adjustable timing circuit as set forth in claim 9 wherein said current source and the means for adjusting the level of the current it provides comprise:

a third transistor having a base and an emitter electrodes with a base-emitter junction therebetween, and having a collector electrode connected to the joined emitter electrodes of said first and said second transistors, its said emitter electrode being coupled to said reference potential;

a unilaterally conductive semiconductor device connected in parallel with said third transistor base-emitter junction;

a source of a biasing potential referred to said reference potential, and means providing an adjustable resistance between said third transistor base electrode and said source of biasing potential.