CODED TIME INDICATING TRANSMISSION SYSTEM

• US 3,811,265 A
• Filed: 01/17/1973
• Issued: 05/21/1974
• Est. Priority Date: 01/17/1973
• Status: Expired due to Term

• Current Assignee: John P. Cater
• Original Assignee: John P. Cater
• Inventors: Cater, John P.
• Primary Examiner(s): Tomsky, Stephen J.
• Assistant Examiner(s): Jackmon, Edith Simmons
• Application Number:
  US05/324,397
• Time in Patent Office: 489 Days
• Field of Search: 58/24-26,33,34,35R 343/225
• US Class Current: 368/48
• CPC Class Codes: G04G 9/0011 using coded signals synchronisation combined with automatic setting at regular intervals, e.g. by coded signals G04G7/00
• CPC Class Codes: H04B 2203/542 using zero crossing information
• CPC Class Codes: H04B 2203/5458 Monitor sensor; Alarm systems
• CPC Class Codes: H04B 3/54 Systems for transmission via power distribution lines

Abstract

Time indicating signals are transmitted from a master clock at a central station to a slave clock at a peripheral station via a two-wire line as binary values represented by pulsed duration modulated signals. Clock, coding and transmitting circuitry at the central station are normally energized by an a.c. power line source. In the event of failure of the a.c. power source, the clock is energized by a battery and transmission from the central station to the remote station ceases. On resumption of power, the first transmission from the central station to the peripheral station enables the slave clock to provide a correct time indication. Transmission can be over any existing lines interconnecting the central and peripheral stations, such as a 60-cycle power line, television cable, or a telephone link. If television cable or 60-cycle line is employed, the presence and absence of voltage is indicated by frequency shift keying transmission. Transmission of the time indication requires only a fraction of the total transmission time, and is constant for all time indications, whereby other data signals can be transmitted between the central and peripheral stations.

Claims

1. A system for transmitting timing information from a central station to a slave clock at a peripheral station via a two-wire line between the stations, wherein the timing indication at the peripheral station is automatically restored upon the resumption of power after a power failure has occurred at the central station, comprising:

at the central station;

a master clock, circuitry means responsive to the master clock for periodically deriving a coded signal indicative of the time of day in terms of at least hours and minutes, means responsive to the coded signal for supplying the coded signal to the two-wire line as a serial signal, an a.c. power supply terminal, means responsive to the a.c. power at the a.c. power supply terminal for supplying energizing power to each of (a) the clock circuitry, (b) the coded signal deriving means (c) the means for supplying the coded signal to the line, a battery power supply means, means responsive to a failure of the a.c. power supply for substituting the battery power supply for the a.c. power supply for the clock circuitry and for disabling transmission of the coded signal via the two-wire line;

at the remote station;

decoding means for periodically converting the time indicating serial signal transmitted via the two-wire line into an indication of time of day in terms of at least hours and minutes, and means for activating the slave clock in response to the converted signal.

2. The system of claim 1 wherein each time indication has a duration less than the period between adjacent time transmissions, and further including:

another coded signal source, and means for enabling signals from said another source to be transmitted on said line only in the interval between the end of a first time code indication and the beginning of the next time code indication.

3. The system of claim 1 wherein the means for periodically deriving includes means for deriving a pulse duration modulated signal indicative of binary coded values for the time of day, said modulated signal having first and second voltage levels, said means for supplying includes means for respectively deriving first and second frequencies in response to the first and second voltage levels.

4. The system of claim 1 wherein the means for periodically deriving includes means for deriving a pulse duration modulated signal indicative of binary coded values for the time of day, said modulated signal having first and second voltage levels, means for periodically inserting a sync pulse having one of said levels between adjacent code indicating pulses, said sync pulse having a duration different from the durations of the pulses indicative of binary coded values.

5. The system of claim 4 wherein the coded signal for each time indication includes the same predetermined number of binary bits representing the coded time signal and the sync pulse, and the decoding means includes a shift register, means for loading said register with first binary values of the signal to the exclusion of second binary values of the signal, means for shifting the signal loaded in the register in response to every binary bit and sync pulse of the signal, and means for reading out data indicating bits, to the exclusion of the sync bits, from the register to the slave clock.

6. The system of claim 5 wherein the shift register has a number of stages equal to the number of data indicating bits between adjacent sync pulses plus one, a binary storage circuit for each value indicating bit of the signal, means for simultaneously transferring binary data indicating bits stored in the register to several of said storage circuits while decoupling the remainder of the storage circuits from the bits stored in the register, said means for transferring being sequentially activated so that each of the storage circuits is responsive to a bit stored in the register during each time indicating signal.

7. The system of claim 4 wherein said means for supplying includes means for respectively deriving First and second frequencies in response to the first and second voltage levels, and the peripheral station includes means for converting said frequencies into a serial signal having a pair of voltage levels.

8. The system of claim 1 wherein the coded signal for each time indication includes the same predetermined number of binary bits, and the decoding means includes a shift register having a number of stages less than the number of bits in the signal, means for loading said register with first binary values of the signal to the exclusion of second binary values of the signal, means for shifting the signal loaded in the register in response to every binary bit of the signal, a binary storage circuit for each value indicating bit of the signal, and means for simultaneously transferring binary bits stored in the register to several of said storage circuits while decoupling the reaminder of the storage circuits from the bits stored in the register, said means for transferring being sequentially activated so that each of the storage circuits is responsive to a bit stored in the register during each time indicating signal.

9. A system for transmitting timing information from a master clock at a central station to a slave clock at a peripheral station via a two-wire line between the stations, said line carrying signals other than the time information or power between the stations, comprising:

at the central station;

circuitry means responsive to the master clock for periodically deriving a binary coded serial signal indicative of time of day in terms of at least hours and minutes, means responsive to the serial signal for deriving a pulse duration modulated signal indicative of binary coded values for the time of day, said modulated signal having first and second voltage levels, means for respectively deriving first and second frequencies in response to the first and second voltage levels, and means for applying said frequencies to the line;

said peripheral station including;

means for converting the first and second frequencies into a pair of voltage levels to derive a received pulse duration modulated serial data signal, and means for driving the slave clock in response to the received serial data signal.

10. The system of claim 9 wherein each time indication has a duration less than the period between adjacent time transmissions, and further including a coded signal source, and means for enabling signals from said coded signal source to be transmitted as a further frequency on said line only in the interval between the end of a first time code indication and the beginning of the next time code indication.

11. The system of claim 9 further including means for periodically inserting a sync pulse having one of said levels between adjacent code indicating pulses, said sync pulse having a duration different from the durations of the pulses indicative of binary coded values.

12. The system of claim 11 wherein the coded signal for each time indication includes the same predetermined number of binary bits representing the coded time signal and the sync pulse, and the decoding means includes a shift register, means for loading said register with first binary values of the signal to the exclusion of second binary values of the signal, means for shifting the signal loaded in the register in response to every binary bit and sync pulse of the signal, and means for reading out data indicating bits, to the exclusion of the sync bits, from the register to the slave clock.

13. The system of claim 12 wherein the shift register has a number of stages equal to the number of data indicating bits between adjacent sync pulses plus one, a binary storage circuit for each value indicating bit of the signal, means for simultaneously transferring binary data indicating bits stored in the register to several of said storage circuits while decoupling the remainder of the storage circuits from the bits stored in the register, said means for transferring being sequentially activated so that each of the storage circuits is responsive to a bit stored in the register during each time indicating signal.

14. The system of claim 9 wherein the coded signal for each time indication includes the same predetermined number of binary bits, and the decoding means includes a shift register having a number of stages less than the number of bits in the signal, means for loading said register with first binary values of the signal to the exclusion of second binary values of the signal, means for shifting the signal loaded in the register in response to every binary bit of the signal, a binary storage circuit for each value indicating bit of the signal, and means for simultaneously transferring binary bits stored in the register to several of said storage circuits while decoupling the remainder of the storage circuits from the bits stored in the register, said means for transferring being sequentially activated so that each of the storage circuits is responsive to a bit stored in the register during each time indicating signal.

15. A central station for transmitting timing information from a master clock to a slave clock at a peripheral station via a two-wire line between the stations, wherein the timing indication at the peripheral station is automatically restored upon the resumption of power after a power failure has occurred, comprising:

circuitry means responsive to the master clock for periodically deriving a coded signal indicative of the time of day in terms of at least hours and minutes, means responsive to the coded signal for supplying the coded signal to the two-wire line as a serial signal, an a.c. power supply terminal, means responsive to the a.c. power supply terminal for supplying energizing power to each of (a) the clock circuitry, (b) the coded signal deriving means and (c) the supplying means, a battery power supply means, means responsive to a failure of the a.c. power supply for substituting the battery power supply for the a.c. power supply for the clock circuitry and for disabling transmission of the coded signal via the two-wire line.

16. A peripheral receiving station for displaying time information transmitted from a central station as a serial binary bit data signal indicative of time of day in terms of at least hours and minutes, said signal including sync pulses periodically inserted between adjacent data pulses, binary values of said data bits being represented as pulses having first and second durations, said sync pulses being represented as pulses having a third duration, the same number of data and sync pulses being included in each time of day indication, comprising a slave clock, a shift register, means for loading said register with first binary values of the signal to the exclusion of second binary values of the signal, means for shifting the signal loaded in the register in response to every binary bit and sync pulse of the signal, and means for reading out data indicating bits, to the exclusion of the sync bits, from the register to the slave clock.

17. The station of claim 16 wherein the shift register has a number of stages equal to the number of data indicating bits between adjacent sync pulses plus one, a binary storage circuit for each value indicating bit of the signal, means for simultaneously transferring binary data indicating bits stored in the register to several of said storage circuits while decoupling the remainder of the storage circuits from the bits stored in the register, said means for transferring being sequentially activated so that each of the storage circuits is responsive to a bit stored in the register during each time indicating signal.

18. The station of claim 16 wherein said signal includes first and second frequencies respectively representing the absence and presence of a pulse, and further including means for detecting said frequencies to derive first and second voltage levels respectively responsive to the first and second frequencies and indicative of the binary values.

19. The station of claim 18 wherein the shift register has a number of stages equal to the number of data indicating bits between adjacent sync pulses plus one, a binary storage circuit for each value indicating bit of the signal, means for simultaneously transferring binary data indicating bits stored in the register to several of said storage circuits while decoupling the remainder of the storage circuits from the bits stored in the register, said means for transferring being sequentially activated so that each of the storage circuits is responsive to a bit stored in the register during each time indicating signal.