SEQUENTIAL CONTROL CIRCUIT HAVING IMPROVED FAULT DETECTION AND DIAGNOSTIC CAPABILITIES

• US 3,812,337 A
• Filed: 04/06/1973
• Issued: 05/21/1974
• Est. Priority Date: 04/06/1973
• Status: Expired due to Term

• Current Assignee: AG Communication Systems Corp. (Nokia Corporation)
• Original Assignee: Thomas Whitley Crosley
• Inventors: Crosley, Thomas Whitley
• Primary Examiner(s): Morrison, Malcolm A.
• Assistant Examiner(s): Dildine, Jr., R. Stephen
• Application Number:
  US05/348,806
• Time in Patent Office: 410 Days
• Field of Search: 179/175.2R 235/153A,153AC,153AK,153AP,92GD,92MC,92EC 340/146.1AB
• US Class Current: 714/811
• CPC Class Codes: G06F 11/085 using codes with inherent redundancy, e.g. n-out-of-m codes
• CPC Class Codes: G06F 11/277 with comparison between actual response and known fault-free response
• CPC Class Codes: H04M 3/24 with provision for checking the normal operation
• CPC Class Codes: H04Q 3/54591 Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis

Abstract

This invention relates to the architecture, fault detection and diagnostic capabilities of a sequential control circuit, or sequencer. The sequential control circuit can be instructed to test any of a number of circuits by executing one of several fixed sequences. The advance from one state to the next in the sequence is dependent on a combination of external signals from the circuit under test, the present sequence state, and the test mode. The new sequence state, in combination with the test mode, cause various actions to take place to further exercise the unit under test.

Claims

1. In combination, a sequence state counter for providing a plurality of output sequence states in consecutive fashion, means for providing a decode of each of said plurality of output sequence states, at least one and only one of said decodes normally being high, an error detection arrangement for detecting errors in the decode of said output sequence states, said arrangement comprising means for detecting and providing a first alarm whenever the decodes of all of said output sequence states are low, means for detecting and providing a second alarm whenever more than one of the decodes of said output sequence states are high, and means for detecting and providing a third alarm whenever the decodes of all of said output sequence states are high simultaneously whereby an alarm is provided whenever less than or more than one decode is high to thereby indicate an erroneous decode of the output sequence state of said sequence state counter.

2. The combination of claim 1, wherein said error detection arrangement comprising a serial 1/N circuit, said first alarm being derived from a serial chain that starts with the decode of the highest output sequence state and is carried through all of the decodes to the decode of the lowest sequence state, whereby any decode going high causes that portion of the serial chain above that decode to the output to go high, said first alarm being provided whenever the decode of all of said output sequence states are low.

3. The combination of claim 2, wherein said serial 1/N circuit comprises a plurality of gates, one input to each of said gates being from an associated decode and another input thereof being said first alarm signal.

4. The combination of claim 2, wherein said sequence state counter has a passive state and an active state, said combination further including means operable during each passive state of said sequence state counter to simulate the decode of all of said output sequence state being low, whereby said means for detecting and providing said first alarm is continually checked during each passive cycle of said sequence state counter.

5. The combination of claim 4, wherein said combination further includes means operable during each passive state of said sequence state counter to simulate the decode of all of said output sequence states being high simultaneously, whereby said means for detecting and providing said third alarm is continually checked during each passive cycle of said sequence state counter.

6. The combination of claim 3, wherein said error detection arrangement further comprises a gate across the inputs of each of said plurality of gates forming said serial 1/N circuit, the outputs thereof comprising said second alarm, whereby if more than one decodes goes high at the same time, the output of one or more of said gates goes low, causing said second alarm.

7. The combination of claim 6, wherein all of said second alarms outputs of said gates are OR'"'"''"'"'ed together to provide said second alarm.

8. The combination of claim 6, wherein each of said gates across the inputs of each of said plurality of gates forming said serial 1/N circuit comprises an AND gate.

9. The combination of claim 6, wherein said error detection arrangement further includes means for inverting the outputs of each of said gates across the inputs of each of said plurality of gates forming said serial 1/N circuit, said inverted outputs being AND'"'"''"'"'ed together to form said third alarm, whereby said third alarm is provided when all of said decodes are high simultaneously.

10. The combination of claim 4, wherein said sequence state counter when in said active state checks for the absence of said first second and third alarms before advancing its output sequence state.

11. The combination of claim 1, wherein said sequence state counter is based on the walking gray code which yields 2n legal states from n flip-flops and 2n-2n illegal states, only one bit of the output walking gray code thereof changing between any two consecutive states, encoding means comprising a plurality of gates for encoding the output walking gray code into a decimal code, said decimal decode being divided in two halves forming an up-half and a down-half in a manner such that a single fault in the input to said encoding means will always cause three decodes to be simultaneously high, said three decodes being simultaneously high operating said means for detecting and providing said second alarm, whereby an indication of said erroneous decode is provided.

12. The combination of claim 11, wherein said encoding means in the event of a fault in the input thereto will always cause three decodes to be simultaneously high, said three decodes resulting in two of said decodes being on one of said up-half and down-half and one of said decodes being on the other one of said up-half and down-half.

13. The combination of claim 12, further including means for disabling either said up-half decode or said down-half decode, said second alarm being removed when said one up-half or down-half having said two decodes is disabled, whereby the fault can be isolated to only those gates of said encoding means providing said one decode.

14. The combination of claim 1, further including advance logic comprising a plurality of input AND gates and a plurality of output OR gates, the outputs of said AND gates being OR'"'"''"'"'ed through established ones of said OR gates to provide an appropriate output to said sequence state counter to advance its output sequence state, said AND gates each having an equal number of inputs and said inputs being accessible via buses, and means for making all but one of said inputs of each of said AND gates high, whereby a stuck 1 on any of said inputs to any one of said AND gates can be detected and located by said stuck 1 causing an erroneous request for said sequence state counter to advance its sequence state.

15. The combination of claim 14, wherein the arrangement of said advance logic is such tht a stuck 0 fault at the input of one of said OR gates will result in a test of said OR gate not providing an output to said sequence state counter to advance its sequence state, and a stuck 1 at the input of one of said OR gates will cause a constant request for said sequence state counter to advance its sequence state.

16. The combination of claim 15, wherein said struck 1 at the input of one of said OR gates normally is detected by said means for detecting and providing said second alarm.

17. The combination of claim 15, wherein a stuck 0 on the input of one of said AND gates will result in a test of said AND gate not requesting said sequence state counter to advance its sequence state.

18. The combination of claim 1, wherein the conditions for a particular sequence state advance of said sequence state counter depend on a combination of various predetermined signals and instructions, further comprising A/B compare logic including a plurality of AND gates for AND'"'"''"'"'ing together said various predetermined signals to provide output logic equations necessary for various sequence state advances, and advance logic including a plurality of AND gates for AND'"'"''"'"'ing together various ones of said logic equations and said instructions to provide an appropriate output to said sequence state counter to advance its sequence state.

19. The combination of claim 18, wherein the arrangement of said A/B compare logic and said advance logic permits the same combination of various predetermined signals to be AND'"'"''"'"'ed together and used by said advance logic with different ones of said instructions.

20. The combination of claim 18, wherein said A/B compare logic is formed by duplicating said AND gates and OR'"'"''"'"'ing the outputs thereof back together, one or the other of said AND gates being selected in sequence and the output thereof being checked to be the same as the output of the other one of said AND gates.

21. The combination of claim 20, further including means alternately operated to enable one or the other of said AND gates, whereby each sequence state advance is initiated with an opposite set of logic.

22. In combination, a sequence state counter for providing a plurality of output sequence states in consecutive fashion, said sequence state counter being based on the walking gray code which yields 2n legal states from n flip-flops and 2n2n illegal states, only one bit of the output walking gray code thereof being changed between any two consecutive states, encoding means comprising a plurality of gates for encoding the output walking gray code into a decimal code, said decimal code being divided in two halves forming an up-half and a down-half in a manner such that a single fault in the input to said encoding means will always cause three decodes to be simultaneously high, and means for detecting and providing an alarm when three decodes are simultaneously high, whereby an indication of an erroneous decode is provided.

23. The combination of claim 22, wherein said encoding means in the event of a fault in the input thereto will always cause three decodes to be simultaneously high, said three decodes resulting in two of said decodes being on one of said up-half and down-half and one of said decodes being on the other one of said up-half and down-half.

24. The combination of claim 23, further including means for disabling either said up-half decode or said down-half decode, said alarm being removed when said one up-half or down-half having said two decodes is disabled, whereby the fault can be isolated to only those gates of said encoding means providing said one decode.

25. The combination of claim 22, wherein said sequence state counter comprises a plurality of input AND gates, and wherein said encoding means comprises a plurality of gates for encoding the output walking gray code of said sequence state counter into decimal code and for providing two duplicate outputs of the decode, said encoding means including an error detection arrangement for detecting errors in the decode of said output sequence states of said sequence state counter, one of said two duplicate outputs of the decode being coupled to said error detection arrangement, advance logic comprising a plurality of input AND gates and a plurality of output OR gates, the outputs of said AND gates being OR'"'"''"'"'ed through established ones of said OR gates to provide an appropriate regular advance output to said input and gates of said sequence state counter to advance its output sequence state, said AND gates each having an equal number of inputs and said inputs being accessible via buses, the other one of said two duplicate outputs of the decode forming a test advance output and being coupled as inputs to both said advance logic and said sequence state counter, and means for enabling said input AND gates of said sequence state counter to accept said test advance output to advance its output sequence state and to block said regular advance output from said advance logic, whereby said sequence state counter can be routined to check its operation.