MEMORY CONTROL FOR TOLL SYSTEMS

• US 3,813,495 A
• Filed: 12/11/1972
• Issued: 05/28/1974
• Est. Priority Date: 12/11/1972
• Status: Expired due to Term

• Current Assignee: Alcatel SA (Nokia Corporation)
• Original Assignee: Howard Jeffery Conerly
• Inventors: Conerly, Howard Jeffery
• Primary Examiner(s): Claffy, Kathleen H.
• Assistant Examiner(s): Brigance, Gerald
• Application Number:
  US05/313,674
• Time in Patent Office: 533 Days
• Field of Search: 179/7MM,9,7R,7.1TP,8R
• US Class Current: 379/128
• CPC Class Codes: H04M 15/04 Recording calls , or communications in printed, perforated or other permanent form

Abstract

A control system for recording toll information is disclosed for use with automatic toll systems for station-to-station telephone calls. The control system employs electronic logic circuits which, in response to signals generated in other components of the system, enable records to be made in the core memory relating to billing data including the identity of the calling party and the time during which a call is established. The core memory empties into a tape memory periodically after the recorded data has been checked for accuracy.

Claims

1. A system for controlling recording apparatus for a toll switching system comprising:

core memory control means for receiving demand signals which indicate a requirement that data be recorded from a switching system, said core memory control means including a first control circuit and a second control circuit, said first control circuit responding to receipt of said demand signals to supply a core enable signal when a core memory is available for recording, means coupling said second control circuit to receive a clock signal from said first control circuit when the core is available for recording, said second control circuit including means providing a pulse to prepare a core memory to receive data, data input terminal means coupled to receive data for recording in a core memory, said first control circuit including a core dump circuit and a tape control circuit, and said second control circuit including write command and read command circuits for providing control signals to operate a core memory.

2. A system as claimed in claim 1, including a label circuit coupled to the data output line of said core memory, said label circuit including scanner means to provide an appropriate label for recording in said tape unit at the beginning of a billing period for recording in said tape unit at the end of the billing period and to indicate a transfer from one type to another.

3. A system as claimed in claim 2, in which the label circuit includes means for generating label information including the month, day, hour, minute and tenth of a minute.

4. A system for controlling recording apparatus for a toll switching system comprising:

core memory control means for receiving demand signals which indicate a requirement that data be recorded from a switching system, said core memory control means including a first control circuit and a second control circuit, said first control circuit responding to receipt of said demand signals to supply a core enable signal when a core memory is available for recording, means coupling said second control circuit to receive a clock signal from said first control circuit when the core is available for recording, said second cOntrol circuit including means providing a pulse to prepare a core memory to receive data, data input terminal means coupled to receive data for recording in a core memory, an address comparison circuit coupled to a core memory for comparing the address of data being recorded in the core memory with a predetermined address, said address comparison circuit providing a cut-off signal to the first control circuit when there is coincidence in the addresses, said first control circuit responding to said cut-off signal to remove the core enable signal and prevent the receipt of further data over the data input terminal means, and said address comparison circuit providing stop tape signals to stop a magnetic tape unit when there is coincidence in the addresses.

5. A system as claimed in claim 4, in which the first control circuit responds to said cut-off signal to supply a reset signal through write and read signal means to the core memory causing the core memory to appear busy and setting the core memory in a random sequence to read out recorded data over a data output line to a tape memory.

6. A system as claimed in claim 4, including a tape control circuit coupled responsive to said demand signals to provide a run normal speed signal to a magnetic tape unit and responsive to said cut-off signal to cut-off said run normal speed signal.

7. A system as claimed in claim 5, including a parity check circuit for checking parity of data read out of the core memory and in the event of parity failure causing a signal indicating '"'"''"'"''"'"''"'"'no data'"'"''"'"''"'"''"'"' to be read onto the tape.