MULTIPLE STAGE SAMPLE NORMALIZING AMPLIFIER WITH AUTOMATIC GAIN PREDICTION

• US 3,813,609 A
• Filed: 11/27/1972
• Issued: 05/28/1974
• Est. Priority Date: 11/27/1972
• Status: Expired due to Term

• Current Assignee: Halliburton Geophysical Services, Inc. (Baker Hughes Company)
• Original Assignee: Alan Fred Sedgwick, Charles Larry Thompson, Don Earl Wilkes
• Inventors: Wilkes, Don Earl, Thompson, Charles Larry, Sedgwick, Alan Fred
• Primary Examiner(s): Saalbach, Herman Karl
• Assistant Examiner(s): Mullins, James B.
• Application Number:
  US05/309,653
• Time in Patent Office: 547 Days
• Field of Search: 330/29,51,86,124,127,151 340/15.5GC
• US Class Current: 330/51
• CPC Class Codes: H03G 3/3026 the gain being discontinuously variable, e.g. controlled by switching

Abstract

A series of fixed gain amplifier stages is selectively coupled by respective electronic switch means to pick-off amplifier means A comparison circuit is coupled between the output of each amplifier stage and amplifier control means. The amplifier control means includes a gain range control circuit which allows the amplifier to gain range continuously during selected portions of a given channel time period, i.e., continuously which selects the highest possible amplifier gain at which the amplifier output is in a linear region. The stages are continuously and selectively coupled to the pick-off amplifier means by the electronic switch means, in response to the gain range control circuit. The control means further includes a rate gain computer circuit coupled to the gain range control circuit and to an analog-to-digital converter, wherein the rate gain computer circuit provides gain prediction means for determining the gain of the amplifier at a subsequent selectable data sample time or times. The amplifier is allowed to gain range in response to the gain range control circuit prior to performing the gain prediction process, whereupon the rate gain computer circuit overrides the gain range control circuit and sets the electronic switch means to select the amplifier stage commensurate with the predicted gain prior to taking the data sample.

Claims

1. A high performance gain-ranging amplifier system including a plurality of serially-coupled fixed gain amplifier stages disposed to receive analog signals and to generate normalized data samples via an analog-to-digital converter at optimum amplifier gain while precluding amplifier stage saturation, comprising:

digital amplifier control means coupled to the amplifier stages to digitally detect and set the gain of the amplifier system to normalize data samples taken by the analog-to-digital converter, said amplifier control means including;

gain range control means for continuously detecting the analog signal levels of each amplifier stage during a selected first portion of a channel time period, and for continuously selecting the optimum amplifier gain in response to the detected levels to maintain the amplifier output in a linear region; and

rate gain computer means operatively coupled to the analog-todigital converter and to the gain range control means to take samples of the amplifier system output at selected times within the first portion of the channel time period via the analog-to-digital converter, and to predict and set accordingly the gain of the amplifier system for a subsequent portion of the channel time period for the purpose of taking the normalized data samples.

2. The amplifier system of claim 1, further comprising pickoff amplifier means continuously coupled to a selected stage of the amplifier system in response to the analog signal levels detected by the gain range control means to continuously maintain said optimum amplifier gain, said pickoff amplifier means being coupled to a selected stage in response to the rate gain computer means to set the gain of the amplifier system in accordance with the gain predicted for the remainder of the channel time period during which the normalized data samples are taken by the analog-to-digital converter.

3. The amplifier system of claim 2 wherein said rate gain computer means includes gain prediction means for determining and setting the gain of the amplifier system prior to taking the normalized data samples.

4. The amplifier system of claim 3, further comprising:

switch means operatively coupled between each of the amplifier stages and the pickoff amplifier means for coupling the selected stage to the pickoff amplifier means; and

comparison means coupled to the plurality of amplifier stage outputs to continuously detect the respective analog signal levels of each stage during the selected first portion of the channel time period.

5. The amplifier system of claim 4, further comprising isolation/buffer means for electrically isolating the amplifier stages, said isolation/buffer means including a first unity amplifier defining the input stage to the plurality of amplifier stages and a second unity amplifier disposed between the switch means and the pickoff amplifier means.

6. The amplifier system of claim 5 wherein the gain range control means is coupled to the comparison means to continuously receive the signal levels detected thereby during the selected first portion of the channel time period, said switch means being responsive to the gain range control means to continuously range up and down the amplifier stages to couple the selected stage to the pickoff amplifier means to provide the output within the linear region.

7. The amplifier system of claim 6, wherein the pickoff amplifier means further includes a pickoff amplifier of selected gain and an attenuator means coupled between the second unity amplifier of the isolation means and the pickoff amplifier to define a selected series of gain steps of selected value.

8. The amplifier system of claim 7, wherein the switch means further includes a first plurality of electronic switches operatively coupled to respective outputs of the plurality of amplifier stages, a first common output buss coupled to a selected number of the first plurality of electronic switches, a second common output buss coupled to the remaining electronic switches of the first plurality, and a second plurality of electronic switches coupled between the first and second common output busses and the second unity amplifier of said isolation means.

9. The amplifier system of claim 3, wherein the gain prediction means includes means coupled to the analog-to-digital converter and to the gain range control means for taking first and second samples within the selected first portion of the channel time period to predict the gain for the data samples to be subsequently taken during the subsequent portion of the channel time period and to set the gain of the amplifier system prior to taking the subsequent data samples.

10. The amplifier system of claim 8, further including signal limiting means coupled to each amplifier stage for limiting the maximum amplitude of the output signals therefrom to determine a selected maximum amplitude and to preclude overloading the succeeding amplifier stage.

11. The amplifier system of claim 8, further including feedback null loop means integral with each amplifier stage of said Plurality to determine DC and low frequency AC offset and circuit drift inherent therein and to provide a feedback voltage representative thereof to correct for said offset and drift.

12. An amplifier gain prediction circuit for controlling the gain ranging of a high performance amplifier system including a plurality of serially coupled fixed gain amplifier stages, comprising:

analog-to-digital converter means coupled to the output of the amplifier system; and

digital rate gain computer means operatively coupled from the analog-to-digital converter means to the amplifier system to take first and second samples VA and VB at times TA and TB respectively within a selected channel time period, to predict the gain for at least a data sample VC to be taken at a later time TC, and to set the gain of the amplifier system prior to taking the data sample VC.

13. The gain prediction circuit of claim 12, further including voltage level detector means coupled to the amplifier stages for initially selecting amplifier gain values which keep the output of the amplifier stages in a linear region and for delivering the gain values to said gain computer means.

14. The gain prediction circuit of claim 13, wherein the gain computer means further includes:

storage register means coupled to the analog-to-digital converter means to receive and temporarily store the first sample VA taken at time TA;

an arithmetic unit coupled to said storage register means to receive the stored sample VA, and coupled to the analog-to-digital converter means to receive the sample VB at time TB; and

a voltage-to-gain circuit coupled between the arithmetic unit and the amplifier system to generate an amplifier gain value for setting the amplifier system gain during taking of the sample VC at time TC.

15. The gain prediction circuit of claim 14 wherein said arithmetic unit includes a digital straight line approximation circuit for predicting the gain at time TC from the samples VA and VB.

16. The gain prediction circuit of claim 15, wherein the arithmetic unit further includes:

inverter means coupled to the analog-to-digital converter means for generating a one complement from the sample VA;

arithmetic circuits coupled to the inverter means and to the analog-to-digital converter means for generating a pair of data signals representing the absolute value of selected multiples of the samples VA and VB.

17. The gain prediction circuit of claim 16, wherein the arithmetic circuit include:

multiplier means coupled to the inverter means and to the analog-to-digital converter means for receiving the samples VA and VB respectively therefrom;

adder means coupled to the multiplier means; and

an absolute value coupled between the adder means and the voltage-to-gain circuit.

18. The gain prediction circuit of claim 15, wherein said arithmetic unit further includes:

a second digital straight line approximation circuit for predicting the gain at a time TD between TB and TC from the samples VA and VB;

comparator means coupled to the approximation circuits for comparing the absolute values therefrom; and

logic switch means for introducing the largest of the absolute values from the approximation circuits to the voltage-to-gain circuit in response to the output from the comparator means.