APPARATUS AND METHOD FOR PERFORMING ON LINE-MONITORING AND FAULT-ISOLATION

• US 3,813,647 A
• Filed: 02/28/1973
• Issued: 05/28/1974
• Est. Priority Date: 02/28/1973
• Status: Expired due to Term

• Current Assignee: Northrop Corporation
• Original Assignee: Brian Hum Loo
• Inventors: Loo, Brian Hum
• Primary Examiner(s): Henon, Paul J.
• Assistant Examiner(s): Thomas, James D.
• Application Number:
  US05/336,792
• Time in Patent Office: 454 Days
• Field of Search: 340/172.5,146.2 235/153R,153A,153AC,153AK,151.13,151.3,151.31
• US Class Current: 714/4.11
• CPC Class Codes: G06F 11/273 Tester hardware, i.e. output processing circuits G06F11/263 takes precedence

Abstract

An electronic monitoring apparatus used in on-line performance monitoring and fault-isolation of complex prime systems through a programmed sequence of parameter measurements based on automatic logical decision functions. The monitoring apparatus which may be connected to external equipment is provided with a mechanism for manual selection of any test point on the external system which is to be measured. In addition, the apparatus includes means for displaying identification of the test point thus measured, the measured value thereof, as well as its low limits or its high limits. A timing control circuit in the apparatus permits measurement and comparison of signals from the external system with stored high and low limit tolerance data on a synchronized basis. The apparatus is capable of examining any of a plurality of parameters through test point selection on a controlled random selection basis. The apparatus also provides means for introducing simulation signals into the external system. Selfcheck sub-systems are incorporated into the apparatus to assure proper performance, prior to any monitoring and fault-isolation operations.

Claims

1. An apparatus for automatically monitoring primary signals and secondary signals at a plurality of test points on a system to be tested, and where said system provides primary test point signals from primary aspects of said system at each of said test points and secondary test point signals from secondary aspects of said system at certain of said test points, and which secondary test point signals are associated with and subordinate to the primary test point signals from the test points at which they are provided;

said apparatus comprising;

a. means for receiving test point signals from the system to be tested at selected test points thereon, b. signal conditioning means for selectively generating a single output from said test point signals and converting the output to words of digital data, c. memory means including a section for storing high preestablished tolerance limit data and low pre-established tolerance limit data for comparison against the test point signals provided at said respective test points, and a control function data section, d. comparator means operatively connected to said memory means and said signal conditioning means for comparing each word of digital data as an output of said signal conditioning means with the stored high pre-established tolerance limit data and the stored low pre-established tolerance limit data, e. time control means operatively connected to said signal conditioning means and said memory means for causing said signal conditioning means to select said test point signals in sequence and to enable comparison against said pre-established tolerance limit data and determining whether a signal is within tolerance limits or out of tolerance limits, f. and instruction means operatively connected to said time control means and said comparator means for enabling a determination of whether the next test point signal to be examined is a secondary test point signal associated with a primary test point signal previously examined or a next primary test point signal in sequence and selecting the next of the primary or secondary signals to be examined, said determination and selecting depending upon the respective determination made by said comparator means of the test point signal immediately previously examined.

2. The apparatus of claim 1 further characterized in that said apparatus comprises presentation means for producing a GO or NO-GO condition based on the respective determination made by said comparator means depending on whether said signal is within tolerance limits or out of tolerance limits.

3. The apparatus of claim 2 further characterized in that said presentation means is a visual display means capable of providing a visual display of said GO or NO-GO conditions.

4. The apparatus of claim 3 further characterized in that said display means comprises at least one display member for indicating the magnitude of a test point signal at a test point and at least one display member for indicating the identification of a test point corresponding to a NO GO determination.

5. The apparatus of claim 4 further characterized in that said apparatus comprises means for causing said display means to indicate in sequence the NO GO determinations, if any, from any test points examined in sequence.

6. The apparatus of claim 1 fuRther characterized in that said apparatus comprises sequence control means operating in conjunction with said time control means and said instruction means for enabling selection of a primary test point signal for next examination if a previous primary test point signal was within the tolerance limits established by the high tolerance limit data and the low tolerance limit data and for enabling selection of a secondary test point signal for next examination if the previous primary test point signal was not within the tolerance limits established by the high tolerance limit data and the low tolerance limit data.

7. The apparatus of claim 6 further characterized in that said sequence control means operates in conjunction with said time control means and said instruction means to enable all successive secondary test point signals associated with a primary test point signal to be examined sequentially when previous secondary test point signals are not within the tolerance limits established by the high tolerance limit data and the low tolerance limit data.

8. The apparatus fo claim 7 further characterized in that said apparatus comprise branch and search means which is operatively associated with and operates in conjunction with said sequence control means to enable the determination by said instruction means of whether the next primary test point signal is to be examined sequentially or the successive secondary test point signals associated with a primary test point signal is to be next examined sequentially.

9. The apparatus of claim 1 further characterized in that said time control means permits synchronization of the tolerance limit data with the corresponding word of digital data generated from any test point signal at a sequencing rate of at least of the order of 15 to several hundred test points per second.

10. The apparatus of claim 1 further characterized in that said apparatus comprises display means for selectively indicating any one of the low tolerance limit data, high tolerance limit data, signal magnitude, signal polarity and engineering units for any selected test point, and display means for indicating the identification of the test point.

11. The apparatus of claim 1 further characterized in that said memory means comprises a read only memory, and includes a section containing high tolerance limit data in the form of multi-bit binary words and low tolerance limit data in the form of multi-bit binary words, and where at least one of the bits in each word represents sign and the remaining bits represent magnitude.

12. The apparatus of claim 1 further characterized in that said signal conditioning means comprises an analog-to-digital converter for generating binary information for polarity and amplitude measurement and for generating binary information for pulse rate measurement.

13. The apparatus of claim 1 further characterized in that said time control means comprises a timing pulse generator generating a plurality of separate pulse trains representing test operating conditions, and a sequence control circuit receiving said last named pulse trains and also receiving signals from said instruction means to produce at its output timing control signals.

14. The apparatus of claim 1 further characterized in that said apparatus comprises internal test checking means for automatically initiating a test check of the operation of said apparatus, said test checking means being operatively connected to and receiving outputs from said time control means and said instruction means.

15. The apparatus of claim 1 further characterized in that said apparatus comprises generating means for generating and introducing stimuli signals in the system to be tested to enable the generation of test point signals by the system to be tested and at the test points on the system to be tested.

16. The apparatus of claim 1 further characterized in that said signal conditioning means comprises selector switching means for selectively coupling the genErated test point signals at a plurality of input connections to a single output, and converter means operatively connected to the output of said selector switching means for converting the signals to digital data.

17. A method for automatically monitoring primary signals and secondary signals at a plurality of test points on a system to be tested, and where said system provides primary test point signals from primary aspects of said system to be tested at each of said test points and secondary signals from secondary aspects of said system at certain of said test points, and which secondary test point signals are associated with and subordinate to the primary test point signals from the test points at which they are provided;

said method comprising;

a. generating test point signals from said system, b. selectively coupling the generated test point signals in sequence, c. generating a single output from the selectively coupled test point signals, d. converting selected ones of said coupled signals to words in a digital data format, e. storing pre-established high tolerance limit data and storing pre-established low tolerance limit data in a storage member, f. storing control function data related to the steps of said method in the storage member, g. comparing the words in digital data format from the converted coupled signals with the pre-established high tolerance limit data and the pre-established low tolerance limit data in synchronism with the tolerance limit data delivered from the storage member, h. determining whether the words in digital data format are within the tolerance limits established by the pre-established high tolerance limit data and the pre-established low tolerance limit data upon instruction commands generated in conjunction with the control function data in said storage member, i. generating a GO condition if such words are within such tolerance limits, and generating a NO GO condition if such words are not within such tolerance limits based on said comparison and determination, j. automatically determining whether the next test point signal to be examined is a secondary test point signal associated with a primary test point signal previously examined or a next primary test point signal in sequence, based on said comparison and the generating of the GO or NO GO conditions, and k. automatically selecting the next of the primary or secondary signals to be examined depending on the respective determination of whether previous test point signal generated a GO or NO GO condition.

18. The method of claim 17 further characterized in that the method comprises displaying the magnitude and polarity of a test point signal provided at a test point and displaying a test point identification corresponding to a NO-GO determination for a test signal at such a test point.

19. The method of claim 17 further characterized in that said method comprises selecting a primary test point signal for next examination if the previous primary test point signal was within tolerance limits established by the high and low tolerance limit data corresponding to a GO determination and selecting a secondary test point signal associated with the previous primary test point signal if the primary test point signal was not within tolerance limits established by the high and low tolerance limit data corresponding to a NO GO determination.

20. The method of claim 17 further characterized in that the method further comprises comparing the tolerance limit data with the corresponding word of digital data generated from any test point signal on a synchronized basis at a sequencing rate of at least of the order of fifteen to several hundred test points per second.

21. The method of claim 17 further characterized in that the storage member is a read only memory, and that the method further comprises converting the coupled signals to words in digital data format, and further that the high tolerance limit datA exists in the form of multi-bit binary words and the low tolerance limit data exists in the form of multi-bit binary words, and where at least one of the bits in each word represents sign and the remaining bits represent magnitude.

22. An apparatus for automatically monitoring test point signals at a plurality of test points on a system to be tested, said apparatus comprising:

a. means for receiving test point signals from the system to be tested at selected test points thereon, b. selector switching means operatively connected to said last named means and having a plurality of input connections from said last named means for selectively coupling the generated test point signals to a single output, c. converter means operatively connected to the output of said selector switching means for converting the signals from the single output of said selector switching means to words of digital data, d. memory means including a section for storing high pre-established tolerance limit data and low pre-established tolerance limit data for comparison against the test point signals provided at said respective test points, and a control function data section, e. comparator means operatively connected to said memory means and said converter means for comparing words of digital data from said converter means with stored high pre-established tolerance limit data and the stored low pre-established tolerance limit data, f. time control means generating a first set of time control signals operatively connected as an input to said selector switching means for causing said selector switching means to couple test point signals from said input connections to said converter means in sequence, said time control means generating a second set of time control signals operatively connected as an input to said memory means for causing said memory means to introduce tolerance limit data to said comparator means synchronized with corresponding words of digital data introduced to said comparator means from said converter means, said comparator means thereby enabling comparison of the words of digital data against the tolerance limits established by said high pre-established tolerance limit data and the tolerance limits established by said low pre-established tolerance limit data for determining whether a signal is within tolerance limits or out of tolerance limits, g. instruction means operatively connected to said time control means and said comparator means for determining a selected next test point in sequence to be examined, h. presentation means operatively connected to said comparator means for producing a GO condition or a NO-GO condition depending upon the respective determination by said comparator means, i. and internal test checking means operatively connected to and receiving outputs from said instruction means and said time control means for automatically monitoring and initiating test checks of the operation of said apparatus to establish proper performance.

23. The apparatus of claim 22 further characterized in that said apparatus comprises means for examining the high pre-established tolerance limit data and the low pre-established tolerance limit data from said memory means, one test point at a time, at locations in said memory means corresponding to the respective test points.

24. The apparatus of claim 23 further characterized in that said apparatus comprises second test checking means and includes a test signal generator, and selector switching means is also operatively connected to said second test checking means and receives test signals from said test signal generator.

25. The apparatus of claim 22 further characterized in that said apparatus comprises second test checking means including test signal generating means connected to and provides test signals to said selector switching means, said selector switching means including an individual actuable switch for each of the components in said apparatus to be tested anD which components are operatively connected to the associated individual actuable switch in said second test checking means.

26. The apparatus of claim 22 further characterized in that the test point signals from the system to be tested are plural level test point signals where certain of said test point signals are major test point signals and certain of said test point signals are sub-test point signals, said apparatus comprising means for automatically monitoring each of said major test point signals and automatically monitoring sub-test point signals associated with said major test point signals when said last named major test point signals renders a NO GO condition.

27. The apparatus of claim 22 further characterized in that said internal test checking means comprises a logic malfunction indicator circuit, a plurality of energizable devices, energizable selectively upon a malfunction, and means for automatically stopping the sequences of said apparatus upon a malfunction thereof.

28. The apparatus of claim 22 further characterized in that said time control means permits synchronization of the tolerance limit data with the corresponding word of digital data generated from any test point signal at a sequencing rate of at least of the order of 15 to several hundred test points per second.

29. The apparatus of claim 22 further characterized in that said memory means comprises a read only memory, and includes a section containing high tolerance limit data in the form of multi-bit binary words and low tolerance limit data in the form of multi-bit binary words, and where at least one of the bits in each word represents sign and the remaining bits represent magnitude.

30. In a data acquisition apparatus of the type which monitors signals from an independently operable system and which data acquisition apparatus comprises a memory device containing a section of high pre-established tolerance limit data and low pre-established tolerance limit data establishing tolerance limits for said signals, selector switching means to couple the signals from the independently operable source, conversion means operatively connected to said selector switching means to receive the coupled signals and convert said signals to words of digital data comparator means operatively connected to the conversion means to receive the words of digital data for comparing these words of digital data with the pre-established tolerance limits, timing control means operatively connected to said selector switching means and said memory device to generate such comparison on a synchronized basis, time pulse generating means within said timing control means for generating time control pulses, counter means within said timing control means to initiate start and stop commands, and instruction means operatively connected to said timing control means and said comparator means to select the next of the signals to be examined in sequence;

the improvement comprising first internal test checking means operatively connected to said timing control means for receiving time control pulses from said pulse generating means and start and stop commands from said counter means, and said instruction means also being operatively connected to and generating sequence instruction signals for input to said first internal checking means for automatically monitoring the the operation of said data acquisition apparatus for proper performance, said counter means being operatively connected to said time pulse generating means and issuing a stop command to stop counting during conversion of a coupled signal to a word of digital data, and said counter means issuing a start command and reinitiating counting when such conversion has been completed, second internal test checking means including a plurality of actuable switches associated with said selector switching means, each one of said actuable switches being operatively connected to a component in said apparatus to be test checked on a periodic basis, said second Internal test checking means including test signal generating means operatively connected to and periodically operating said selector switching means for initiating a test check of the components connected to the switches in said selector switching means and for comparing responses to a generated function in said components.

31. The improvement in the data acquisition apparatus of claim 30 further characterized in that said plurality of individual switches are automatically actuable and said test signal generating means is operatively connected to each of said individual switches for selectively initiating a test check of any one or more of the components of said apparatus.

32. The improvement in the data acquisition apparatus of claim 30 further characterized in that said data acquisition apparatus comprises amplifier means operatively interposed between said selector switching means and said comparator means, and wherein said amplifier means scales the coupled signals to a desired range for conversion.

33. The improvement in the data acquisition apparatus of claim 30 further characterized in that said timing control means of said apparatus permits synchronization of the tolerance limit data with the corresponding word of digital data generated from any test point signal at a sequencing rate of at least of the order of 15 to several hundred test points per second.

34. The improvement in the data acquisition apparatus of claim 30 further characterized in that said memory devices comprises a read only memory, and includes a section containing high tolerance limit data in the form of multi-bit binary words and low tolerance limit data in the form of multi-bit binary words, and where at least one of the bits in each word represents sign and the remaining bits represent magnitude.

35. A method for automatically monitoring test point signals in a non-programmable self-contained apparatus and which test point signals are generated at a plurality of test points on an external system to be tested;

said method comprising;

a. generating test point signals from said system, b. selectively coupling in sequence the generated test point signals, c. converting selected ones of said signals to words in digital data format, d. storing high pre-established tolerance limit data and low pre-established limit data to establish high and low tolerance limits in a storage member, e. comparing the tolerance limits established by the high and low tolerance limit data with the words of digital data in sequence and on a synchronized basis with the data delivered from said storage member, presenting a GO or NO GO condition based on said comparison, f. generating timing signal pulses to enable the comparing of the tolerance limit data with the words of digital data on the synchronized basis, g. counting the timing signal pulses as they are generated, h. stopping the counting of the timing signal pulses during the conversion of a signal to a word of digital data format, i. generating a termination signal at the end of the conversion operation and reinitiating the counting of the timing signal pulses, j. generating sequence control signals for normal sequence of operations in said apparatus, k. determining if the stopping of the counting is normal or abnormal in accordance with the sequence control signals to thereby determine if the apparatus is properly operating, l. generating a plurality of test signals and connecting these signals across a plurality of switches which are connected to certain components in said apparatus to be tested, m. and periodically automatically opening and closing said switches to internally check certain of the the components in said apparatus for proper performance.

36. The method of claim 35 further characterized in that the method comprises displaying the magnitude and polarity of a test point signal provided at a test point on the external system and displaying a test Point identification corresponding to a NO GO determination for a test point signal at such a test point.

37. The method of claim 35 further characterized in that certain of the test point signals are major test point signals and certain of the test point signals are sub-test point signals, and wherein the method comprises automatically monitoring each of said major test point signals and automatically monitoring sub-test point signals associated with major test point signals when said last named major test point signal renders a NO GO condition.

38. The method of claim 35 further characterized in that the method further comprises comparing the tolerance limit data with the corresponding word of digital data generated from any test point signal on a synchronized basis at a sequencing rate of at least of the order of fifteen to several hundred test points per second.

39. The method of claim 35 further characterized in that the storage member is a read only memory, and that the method further comprises converting the coupled signals to words in digital data format, and further that the high tolerance limit data exists in the form of multi-bit binary words and the low tolerance limit data exists in the form of multi-bit binary words, and where at least one of the bits in each word represents sign and the remaining bits represent magnitude.

40. An apparatus for automatically monitoring primary signals and secondary signals at a plurality of test points on a system to be tested, and where said system provides primary test point signals from primary aspects of said system at each of said test points and secondary test point signals from secondary aspects of said system at certain of said test points, and which secondary test point signals are associated with and subordinate to the primary test point signals from the test points at which they are provided;

said apparatus comprising;

a. means for receiving test point signals from the system to be tested at selected test points thereon, b. signal conditioning means for selectively generating a single output from said test point signals and converting the output to words of digital data, c. memory means for storing pre-established tolerance limit data for signals at said respective test points, d. comparator means operatively connected to said memory means and said signal conditioning means for comparing each word of digital data as an output of said signal conditioning means with the stored tolerance limit data, e. time control means operatively connected to said signal conditioning means and said memory means for causing said signal conditioning means to select said test point signals in sequence and to enable comparison against said pre-established tolerance limit data and determining whether a signal is within tolerance limits or out of tolerance limits, f. means operatively associated with said time control means to permit synchronization of the tolerance limit data with the corresponding digital data generated from any test point signal at a sequencing rate of at least of the order of 15 to several hundred test points per second, g. and instruction means operatively connected to said time control means and said comparator means for enabling a determination of whether the next test point signal to be examined is a secondary test point signal associated with a primary test point signal previously examined or a next primary test point signal in sequence and selecting the next of the primary or secondary signals to be examined depending upon the respective determination made by said comparator means of the test point signal immediately previously examined.