INTERLOCK CIRCUIT
First Claim
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1. In an interlock circuit for energizing a load from a power source by a control switch not less than a predetermined time after de-enerization of the load the combination of:
- a solid state switch having a control gate for switching to the conducting condition;
means for connecting said solid state switch in circuit between the power source and the load;
a dc power supply having first and second output terminals;
a storage capacitor;
a first transistor having its collector and emitter electrodes connected in series with said capacitor across said output terminals for charging said capacitor;
a resistor circuit connected across said capacitor;
first circuit means connecting a point on said resistor circuit to said control gate;
a second transistor having its collector and emitter electrodes connected between the base of said first transistor and one of said output terminals for controlling current in said first transistor; and
second circuit means connecting said capacitor to the base of said second transistor for controlling current in said second transistor;
with said first transistor conducting, charging said capacitor and developing a control voltage at said point of said resistor circuit, switching said solid state switch to the conducting condition when the control switch is closed and said capacitor is not charged, with said capacitor discharging into said resistor circuit and blocking current in said second transistor and in said first transistor when the control switch is opened, switching said solid state switch to the nonconducting condition and preventing conduction by said first transistor until said capacitor is discharged below a predetermined value.
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Abstract
A circuit for controlling a load, such as the cooling compressor of an air conditioner, to prevent short cycling by utilizing a time delay or interlock after deenergizing a load, before the load can again be energized. An all solid state circuit operable on initial control switch closure to turn on power to the load and charge the capacitor of a time delay circuit, and operable on control switch opening to turn off power and maintain power off despite subsequent control switch closure until the capacitor has discharged through the delay circuit.
23 Citations
4 Claims
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1. In an interlock circuit for energizing a load from a power source by a control switch not less than a predetermined time after de-enerization of the load the combination of:
- a solid state switch having a control gate for switching to the conducting condition;
means for connecting said solid state switch in circuit between the power source and the load;
a dc power supply having first and second output terminals;
a storage capacitor;
a first transistor having its collector and emitter electrodes connected in series with said capacitor across said output terminals for charging said capacitor;
a resistor circuit connected across said capacitor;
first circuit means connecting a point on said resistor circuit to said control gate;
a second transistor having its collector and emitter electrodes connected between the base of said first transistor and one of said output terminals for controlling current in said first transistor; and
second circuit means connecting said capacitor to the base of said second transistor for controlling current in said second transistor;
with said first transistor conducting, charging said capacitor and developing a control voltage at said point of said resistor circuit, switching said solid state switch to the conducting condition when the control switch is closed and said capacitor is not charged, with said capacitor discharging into said resistor circuit and blocking current in said second transistor and in said first transistor when the control switch is opened, switching said solid state switch to the nonconducting condition and preventing conduction by said first transistor until said capacitor is discharged below a predetermined value.
- a solid state switch having a control gate for switching to the conducting condition;
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2. An interlock circuit as defined in claim 1 wherein the rate of discharge of said capacitor through said resistor circuit is less than the rate of charge through said first transistor for maintaining said capacitor charged except when said first transistor is not conducting.
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3. An interlock circuit as defined in claim 2 wherein said second transistor is a normally conducting field effect transistor.
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4. An interlock circuit as defined in claim 3 wherein said solid state switch includes four diodes connected in a full wave configuration with two opposite points for connection to the power source and load, and a controlled rectifier connected across the other two opposite points.
Specification