POLARITY GUARD

• US 3,819,951 A
• Filed: 12/27/1972
• Issued: 06/25/1974
• Est. Priority Date: 11/28/1972
• Status: Expired due to Term

• Current Assignee: Arthur D. Moore
• Original Assignee: Arthur D. Moore
• Inventors: Moore, Arthur D.
• Primary Examiner(s): Rolinec, Rudolph V.
• Assistant Examiner(s): Davis, B. P.
• Application Number:
  US05/318,760
• Time in Patent Office: 545 Days
• Field of Search: 307/202,262,236,127 317/39,43
• US Class Current: 361/77
• CPC Class Codes: H02H 11/002 in case of inverted polarity or connection; with switching for obtaining correct connection
• CPC Class Codes: H02M 7/219 in a bridge configuration
• CPC Class Codes: H02M 7/2195 the switches being synchronously commutated at the same frequency of the AC input voltage
• CPC Class Codes: H04M 1/6008 in the transmitter circuit
• CPC Class Codes: H04M 1/6016 in the receiver circuit
• CPC Class Codes: H04M 19/08 with current supply sources at the substations generating ringing current H04M19/04

Abstract

The invention relates to a polarity guard for insertion between terminals connected across a potential supply and a load means, the input polarity of which load means must be constant regardless of the polarities of the potential supply terminals. The invention has particular application to, but is by no means limited to the field of telephony wherein a transducer must often be capable of operation from a telephone line, the polarity of which is variable but the transducer requiring a constant polarity input. Typical of such a transducer is a headset amplifier for powering an electret or similar microphone in place of the traditional carbon microphone.

Claims

1. A polarity guard having first and second input terminals for connection to a potential supply, and first and second output terminals for connection across a load, said pOlarity guard characterized by first, second, third and fourth transistors, said first and second transistors being of one conductivity type, and said third and fourth transistors being of another conductivity type, the control electrodes of said first and fourth transistors being connected via first and fourth resistors respectively to said first input terminal and the control electrodes of said second and third transistors being connected via second and third resistors respectively to said second input terminal, said first input terminal being connected through said second transistors to said second output terminal and through said third transistors to said first output terminal and said second input terminal being connected through said first transistor to said second output terminal and through said fourth transistor to said first output terminal.

2. The polarity guard as defined in claim 1 characterized in that said first, second, third, and fourth transistors are bipolar transistors, the control electrodes of said first, second, third and fourth transistors being the base electrodes of said first, second, third and fourth transistors.

3. The polarity guard as defined in claim 2 characterized in that the first and second transistors are n.p.n. bipolar transistors and the third and fourth transistors are p.n.p. bipolar transistors.

4. The polarity guard as defined in claim 1 characterized in that the first and second transistors are n.p.n. bipolar transistors, the third and fourth transistors are p.n.p. bipolar transistors, the collector electrodes of the second and fourth transistors being respectively connected to the second and first output terminals, and the emitter electrodes of the first and third transistors being respectively connected to said second and first input terminals.

5. The polarity guard as defined in claim 2 characterized in that the first and second transistors are n.p.n. bipolar transistors, the third and fourth transistors ar p.n.p. bipolar transistors, the collector electrodes of the second and fourth transistors being respectively connected to the second and first output terminals, and the emitter electrodes of the first and third transistors being respectively connected to said second and first input terminals.

6. The polarity guard as defined in claim 1 characterized in that the first and second transistors are N-channel enhancement type field effect transistors and the third and fourth transistors are P-channel enhancement type field effect transistors.

7. The polarity guard as defined in claim 6 characterized in that the control electrodes of said first, second, third and fourth field effect transistors are the gate electrodes of said field effect transistors.