DEVICE FOR TESTING THE OPERATION OF SEQUENTIAL INTEGRATED CIRCUITAL UNITS

• US 3,821,645 A
• Filed: 03/13/1973
• Issued: 06/28/1974
• Est. Priority Date: 03/17/1972
• Status: Expired due to Term

• Current Assignee: Vinsani M
• Original Assignee: Vinsani M
• Inventors: VINSANI M
• Application Number:
  US05/340,798
• Time in Patent Office: 472 Days
• US Class Current: 714/736
• CPC Class Codes: G01R 1/0425 Test clips, e.g. for IC's
• CPC Class Codes: G01R 31/317 Testing of digital circuits
• CPC Class Codes: G01R 31/3193 with comparison between actual response and known fault free response receiver details G01R31/31924

Abstract

A device is provided for testing integrated circuit units, the device including means for connecting the unit under test and comparing the outgoing signal of the unit with the outgoing signal of a reference unit to detect a difference in the logic operation of the unit under test and to determine failures. In order for such comparison to be accomplished, the reference unit is placed in the same state in which the unit under test should be for correct operation. The present device is advantageously employed in testing those units having circuit elements capable of assuring one of two definite states, and remaining in that state for an indefinite length of time.

Claims

1. An improved test device for electronic circuit units, having a plurality of input and output leads, and mounted on digital electronic apparatus, comprising a reference circuit unit similar to the circuit unit under test, at least a comparator circuit having two input and one output leads, means for temporarily and singularly connecting each input lead of a circuit unit under test to the corresponding lead of the reference circuit unit, and for connecting at least one output lead of said circuit unit under test to a first input lead of said comparator circuit;

means for connecting the corresponding output lead of the reference circuit unit to the second input lead of said comparator circuit, the comparator circuit delivering a discordance signal whenever two signals of different binary level are applied to the input leads of said comparator circuit;

timing means for transmitting only the discordance signals exceeding a predetermined time interval;

means for memorizing the transmitted discordance signal, and means controlled by said memorizing means, for emitting an alarm signal, the improvement comprising a supervision circuit having input leads for receiving at least part of the signals applied to the input leads of the unit under test, and means for inhibiting the memorizing of said dicordance signal under control of signals delivered by said supervision circuit, said supervision circuit disabling said inhibiting means when the reference unit has received all signals needed for setting all memory elements comprised therein in the same state as the memory elements comprised in the unit under test in case of correct operation of the unit under test in response to the received signals.

2. An improved test device as claimed in claim 1 wherein said signals received by said supervision circuit are at least part of the signals applied to the circuit unit under test for controlling the memory elements comprised therein.

3. An improved test device as claimed in claim 2, wherein said supervision circuit comprises memory elements controlled by at least part of said signals applied to the circuit unit under test for controlling the memory elements comprised therein.

4. An improved test device as claimed in claim 2, wherein the signals applied to the reference unit for controlling the memory elements comprised therein are under the control of said supervision unit, said supervision unit being able to inhibit the receiving of at least part of said signals under control of the discordance signal, for modifying the progression of the set of memory elements of the reference unit along a succession of state combinations, for reaching a condition whereby the set of memory elements contained in the unit under test and the set of memory elements contained in the reference unit are in the same combination of states.

5. An improved signal device as claimed in claim 4, wherein the inhibiting of the memorizing of the discordance signal is disabled by the supervision unit after a predetermined time interval from the beginning of the test of the unit under test.