MEMORY SYSTEM FOR A MULTI CHIP DIGITAL COMPUTER

• US 3,821,715 A
• Filed: 01/22/1973
• Issued: 06/28/1974
• Est. Priority Date: 01/22/1973
• Status: Expired due to Term

• Current Assignee: Faggin F, Hoff M, Mazor S
• Original Assignee: Faggin F, Hoff M, Mazor S
• Inventors: FAGGIN F, HOFF M, MAZOR S
• Application Number:
  US05/325,511
• Time in Patent Office: 522 Days
• US Class Current: 711/1
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 15/7864 on more than one IC chip

Abstract

A general purpose digital computer which comprises a plurality of metal-oxide-semiconductor (MOS) chips. Random-access-memories (RAM) and read-only-memories (ROM) used as part of the computer are coupled to common bi-directional data buses to a central processing unit (CPU) with each memory including decoding circuitry to determine which of the plurality of memory chips is being addressed by the CPU. The computer is fabricated using chips mounted on standard 16 pin dual in-line packages allowing additional memory chips to be added to the computer.

Claims

1. A general purpose digital computer comprising:

a central processor disposed on a first semiconductor chip;

a plurality of bidirectional data bus lines;

at least a separate first and second semiconductor memory chip each defining a memory and each including a chip decoding circuit for recognizing a different predetermined code on said bidirectional data bus lines and for activating a portion of said memory upon receipt of said predetermined code, said data bus lines interconnecting said processor and said first and second memory chips for communicating said different predetermined codes from said processor to at least one of said first and second memory chips and for communicating data signals for one of said first and second memory chips to said processor;

whereby said processor may communicate signals to said first and second memory chips and said decoding circuits shall determine which memory is being addressed.

2. The computer defined in claim 1 wherein at least one of said first and second memory chips comprises a read-only-memory.

3. The computer defined in claim 1 wherein said processor includes circuit means for first communicating a signal representative of a location in one of said first and second memory chips and secondly communicates a coded signal which corresponds to said predetermined code recognized by one of said decoding circuits of said first and second memory chips.

4. The computer defined in claim 3 wherein said first memory chip comprises a read-only-memory and said second memory chip comprises a random-access-memory.

5. The computer defined in claim 4 wherein said random-access-memory comprises dynamic storage devices.

6. The computer defined in claim 5 wherein instructions for said computer are stored in said read-only-memory.

7. The computer defined in claim 5 wherein said random-access-memory includes means for refreshing said dynamic storage devices.

8. The computer defined in claim 7 wherein said refreshing means includes a counter for selecting a portion of said random-access-memory for refreshing.

9. The computer defined in claim 8 wherein said refreshing means includes means for advancing said counter.

10. The computer defined in claim 6 wherein the contents of said read-only-memory and said chip decoding circuit of said read-only-memory are defined by masks used to fabricate said read-only-memory.

11. The computer defined in claim 4 wherein said central processor communicates timing signals to said first and second memory chips, said timing signals defining a first period during which communications occur between said central processor and at least one of said first and second memory chips and a second period during which at least a portion of said random-access-memory is refreshed.

12. A digital computer comprising:

a first MOS chip which includes a central processor;

at least one MOS read-only-memory disposed on a second chip which includes a read-only-memory and chip recognition circuitry for recognizing a first predetermined coded signal and for enabling said memory chip to transmit a stored signal upon recognition of said first predetermined coded signal;

at least one MOS random-access-memory disposed on a third chip which includes a random-access-memory and chip recognition circuitry for recognizing a second predetermined coded signal and for enabling access to said random-access-memory upon recognition of said second predetermined coded signal;

a plurality of data lines interconnecting said central processor chip and said memory chips for communicating said first and second predetermined coded signals to said memories and for transmitting stored signals to and from said memories;

whereby said processor may selectively communicate with one of said memories.

13. A general purpose digital computer comprising:

an MOS central processing chip for performing central processing for said computer;

a plurality of MOS read-only-memory (ROM) chips, distinct from said processing chip, each including a read-only-memory for storing computer instructions and each ROM chip including a chip select code circuit for recognizing a different predetermined code and for enabling said ROM chips to transmit stored information upon recognition of its code such that no more than one of said plurality of ROM chips shall transmit stored information at any given time;

a plurality of MOS random-access-memory (RAM) chips distinct from said processing chip and said ROM chips, each including a random-access-memory for storing information and each RAM chip including a chip select code circuit for recognizing a different predetermined code and for enabling said RAM chips to be accessed upon recognition of its code such that no more than one of said plurality of RAM chips shall be accessed at any given time;

a plurality of common data lines each interconnecting said central processor, said ROM chips and said RAM chips for transmitting said different predetermined codes and for transmitting data from said memories to said processing chip;

whereby said central processor is able to communicate with only a selected one of said ROM chips and RAM chips on said common lines.

14. The computer defined in claim 13 wherein at least some of said RAM chips are coupled to a common line which provides a continuous signal which form a part of said predetermined code.

15. The computer defined in claim 13 wherein said RAM chips comprise dynamic storage devices.

16. The computer defined in claim 15, including four common data lines.

17. The computer defined in claim 13 wherein at least some of said ROM chips and RAM chips include ports for receiving input signals to said computer and for providing output signals from said computer.