BOOSTER CIRCUIT

• US 3,824,447 A
• Filed: 11/30/1972
• Issued: 07/16/1974
• Est. Priority Date: 12/03/1971
• Status: Expired due to Term

• Current Assignee: Tsuneo Kuwabara
• Original Assignee: Tsuneo Kuwabara
• Inventors: Kuwabara, Tsuneo
• Primary Examiner(s): Shoop, Jr., William M.
• Application Number:
  US05/310,911
• Time in Patent Office: 593 Days
• Field of Search: 307/109,110 321/15
• US Class Current: 363/60
• CPC Class Codes: G04G 19/04 Capacitive voltage division or multiplication
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03K 17/063 in field-effect transistor switches

Abstract

A booster circuit is provided which comprises a booster output capacitor and a plurality of capacitors, which are connected in parallel to a booster power supply for being charged when a voltage of a first level is applied to an input terminal of the booster circuit and, on the other hand, connected in series with each other when a voltage of a second level is applied thereto. The alternate application of the voltages having the first and second levels in repetitive manner allows the generation of a boosted voltage across the booster output capacitor.

Claims

1. A booster circuit comprising a plurality of complementary field effect transistor elements each including P type and N type complementary field effect transistors having source, drain and gate terminals in drain-to-drain and gate-to-gate configuration;

a booster power supply for supplying a voltage to the source terminals of said N type complementary field effect transistors;

an input terminal connected to the gate terminals of said complementary field effect transistors for controlling the output of said each complementary field effect transistor element;

signal means for applying to said input terminal a voltage having first and second alternately appearing levels;

a plurality of capacitors one terminal of which is connected to the drain terminal of one of said complementary field effect transistor elements and the other of which is connected to the source terminal of the following P type complementary field effect transistor and to the gate terminal thereof and said input terminal through a diode, said capacitors being thereby connected in parallel to said power supply and charged when said voltage with the first level is applied to said input terminal and being connected in series with each other and with said power supply when said voltage with the second level is applied to said input terminal; and

a booster output capacitor connected in series with said plurality of capacitors and said power supply when said voltage of tHe second level is applied to said input terminal, thereby producing a boosted voltage across said booster output capacitor.

2. A booster circuit comprising a plurality of field effect transistor elements each including two field effect transistors of one polarity having source, drain and gate terminals, a capacitor connected between the source terminal of one of said two field effect transistors and the drain terminal of the other thereof;

a booster power supply for supplying a voltage to the drain terminals of said one of two field effect transistors in said field effect transistor elements;

an input terminal connected to the gate terminals of said field effect transistors for controlling the output of said field effect transistor element;

a second plurality of field effect transistors having source, drain, and gate terminals, the source and drain terminals thereof being connected in series with said plurality of capacitors and said booster power supply, and the gate terminals thereof being connected to said input terminal;

signal means for applying to said input terminal a voltage having first and second alternately appearing levels, said capacitors being thereby connected in parallel to said power supply and charged when said voltage with the first level is applied to the gate terminals of said field effect transistor element and being connected in series with each other and with said power supply when said voltage with the second level is applied to said gate terminals of said second plurality of field effect transistors; and

a booster output capacitor connected in series with said plurality of capacitors and said power supply when said voltage of the second level is applied to said gate terminal of said second plurality of field effect, thereby producing a boosted voltage across said booster output capacitor.