CIRCUIT ARRANGEMENT FOR AUTOMATIC ZERO LEVEL COMPENSATION

• US 3,824,481 A
• Filed: 02/07/1973
• Issued: 07/16/1974
• Est. Priority Date: 02/08/1972
• Status: Expired due to Term

• Current Assignee: Bodenseewerk Perkin-Elmer GmbH (Revvity, Inc.)
• Original Assignee: Hans Kiefer, Richard Sponholz
• Inventors: Sponholz, Richard, Kiefer, Hans
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US05/330,222
• Time in Patent Office: 524 Days
• Field of Search: 328/150,162,163,173,175 330/11SZ 178/7.3DC,7.5DC,7.1,DIG.26,DIG.12
• US Class Current: 327/101
• CPC Class Codes: G01D 3/06 with provision for operation by a null method
• CPC Class Codes: G01D 5/248 by varying pulse repetition frequency
• CPC Class Codes: G01R 19/00 Arrangements for measuring currents or voltages or for indicating presence or sign thereof G01R5/00 takes precedence; for measuring bioelectric currents or voltages A61B5/24

Abstract

A known type of circuit for compensating (i.e. balancing or zeroing) an input signal relative to a changing base line includes a voltage-to-frequency converter receiving the input signal being compensated or balanced, a counter receiving the output pulses of this voltage-to-frequency converter, and a digital-to-analog converter controlled by the counter, where the output of the digital-to-analog converter generates a correction signal which can be added algebraically to the input signal for zero level (base line) compensating or balancing. To shorten the time of balancing without causing overshooting, the present circuit causes coarse adjustment by feeding the output of a (relatively high) fixed frequency generator to the more significant counting stages of the counter until an approximation of balance is reached, followed by feeding the output of the conventional voltage-to-frequency converter to the lesser significant stages after this coarse balancing has been completed. The means for changing over from the coarse balancing to the fine adjustment may include a positive and a negative threshold-value switch.

Claims

1. In a circuit for automatic balancing or compensating of an input signal to a drifting zero base line level including in series relationship a voltage-to-frequency converter to the input of which is applied the input signal being balanced, a counter for counting the output pulses of the voltage-to-frequency converter, and a digital-to-analog converter controlled by the counter, which generates an analog correction signal proportional to the counter reading, which correction signal is algebraically added to the input signal for base line level balancing, the improvement comprising:

that the counter comprises two distinct groups of counter stages, one of said groups consisting of the more significant bit stages and the other of said groups consisting of the less significant bit stages;

a fixed frequency pulse generator, the output of which is connected through a first controllable means to said one group of more significant bit counter stages;

said first controllable means passing the output from said fixed frequency pulse generator to said one group of more significant bit counter stages only when said input signal differs from the desired zero base line level by more than a particular threshold value;

The output of said voltage-to-frequency converter being connected through a second controllable means to said other group of less significant bit counter stages, said second controllable means passing the output of said voltage-to-frequency converter to said other group of less significant bit counter stages only when said input signal has been compensated relative to said desired zero base line level to within said particular threshold value, whereby coarse compensating of said input signal to said desired zero base level is obtained rapidly by the fixed frequency pulses causing the one group of more significant counter stages to store a value proportional to an approximate correction signal to within said threshold value, and then fine compensating of said input signal to said desired zero base line level is obtained from the voltage-to-frequency converter causing said other group of less significant counter stages to be driven at decreasing rate as the partially compensated input signal approaches closer and closer to the desired zero base level, so that rapid balancing of the input signal relative to the desired zero base line level is obtained, but without any overshooting of the desired compensation.

2. A compensating circuit according to claim 1, in which:

said first and second controllable means comprises first and second gating means; and

a threshold-value determining means continuously detects whether the input signal as partially compensated differs from said desired zero base line level by more or less than said particular threshold value, said determining means being operatively connected to said first and second controllable means so as to control said first and second gating means, whereby said first gating means passes pulses only when said particular threshold value is exceeded by, and said second gating means passes pulses only when said particular threshold value is larger than, the difference between said partially compensated input signal and said desired zero base line level.