APPARATUS FOR ALLOCATING STORAGE ADDRESSES TO DATA ELEMENTS

• US 3,824,561 A
• Filed: 12/29/1972
• Issued: 07/16/1974
• Est. Priority Date: 04/19/1972
• Status: Expired due to Term

• Current Assignee: Peter Wolf
• Original Assignee: Peter Wolf
• Inventors: Wolf, Peter
• Primary Examiner(s): Henon, Paul J.
• Assistant Examiner(s): Thomas, James D.
• Application Number:
  US05/319,566
• Time in Patent Office: 564 Days
• Field of Search: 340/172.5 444/1
• US Class Current: 711/219
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words

Abstract

A group of variable length data elements are allocated storage addresses by means of apparatus and an associated method, the allocation taking place before the data elements are stored. Characteristic data sets are provided in a main storage which define the characteristics of each data element in the group. The data sets are scanned in two directions. On the first pass, information as to the lengths and boundary requirements of each element are accumulated. On the second pass, addresses are allocated to each element to eliminate gaps in the group while maintaining proper boundary alignment.

Claims

1. Apparatus for automatically allocating storage addresses to a group of data elements of varying lengths, comprising:

storage means for storing characteristic data sets denoting characteristics of said data elements, each data set containing data fields comprising a length value denoting the length of the associated data element and a characteristic value denoting the boundary type of the associated data element;

a working register connected to said storage means for buffering a characteristic data set;

control means connected to said storage means and said working register for loading said characteristic data sets serially in said working register;

an accumulator register connected to said working register for accumulating each length value from each data set buffered in said working register;

an address computing unit linked with positions of said working register and said accumulator register; and

an address alignment circuit for comparing the contents of said accumulator register with each said characteristic value buffered in said working register and incrementing said contents according to each said characteristic value so as to correspond to the boundary type denoted thereby.

2. Apparatus in accordance with claim 1, wherein said address alignment circuit comprises a masking circuit for the lowest positions of said accumulator register, said masking circuit responding to predetermined bits in each characteristic value;

an incrementing circuit connected to said accumulator register; and

said masking circuit comprising a control signal output for actuating said incrementing circuit and which, in accordance with a logic function, carries a signal as long as there is a predetermined bit in one of the masked positions of said accumulator register.

3. Apparatus in accordance with claim 2 comprising:

a further register for buffering the characteristic value Z'"'"''"'"' of the greatest boundary type of said data elements, means for comparing said characteristic value Z'"'"''"'"' with each characteristic value Z in said working register and means for setting said value Z'"'"''"'"' to a new value corresponding to that of Z whenever the value of Z being compared is greater than that of Z'"'"''"'"'.

4. Apparatus in accordance with claim 3 comprising:

means for selectively coupling said further register with said masking circuit and said incrementing circuit to set the contents of said accumulator register to a storage boundary associated with said group as a start address.

5. Apparatus in accordance with claim 1 wherein said control means comprises:

a push-down storage for storing the addresses of characteristic data sets characterizing substructures of said group of data elements, and addressing means responsive to each address in said push-down storage for loading said data set addressed thereby into said working register.