ANALOG-DIGITAL CONVERTER CIRCUIT

• US 3,824,584 A
• Filed: 05/15/1972
• Issued: 07/16/1974
• Est. Priority Date: 05/15/1972
• Status: Expired due to Term

• Current Assignee: Pasco A. Coia
• Original Assignee: Pasco A. Coia
• Inventors: Coia, Pasco A.
• Primary Examiner(s): Robinson, Thomas A.
• Application Number:
  US05/253,549
• Time in Patent Office: 792 Days
• Field of Search: 340/347CC,347DA,347AD 178/DIG.12 328/48
• US Class Current: 341/120
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: H03M 1/50 with intermediate conversion to time interval H03M1/64 takes precedence

Abstract

An analog-digital converter circuit that converts electrical input signals, representative of such variables as voltage, current or resistance, into time-impulse signals. The converter circuit as disclosed is designed to accept various input signals for example, signals representing values between 0-5 volts, 4-20 milliamps, 10-50 milliamps, 0-25 kilohms. Signals of this character are converted into time-impulse signals whose pulse width is adjusted to be directly proportional with the magnitude of the input signals. When the aforementioned analog input electrical signals are so converted they are then adapted to be transmitted great distances via telephone lines, or radiomicrowave communication links, without distortion. Such form of output signals are adapted for transmission in connection with certain time-impulse telemetering systems, for example, a system known as the Chronoflo system. When used with such Chronoflo system, a 0-5 volt signal would be adjusted to give a 0-13.333 second pulse, whose repetition cycle would be 15 seconds. The converter of the instant invention includes provision for accepting various input signal levels and for modifying the output time-impulse signal to conform to a variety of timeimpulse formats. Another provision which is included is a masking of the input signals which occur below a prescribed level. This masking of input signals below a threshold prevents spurious signal generation due to low level noise at the input.

Claims

1. A circuit for converting analog input electrical signals into time-impulse signals comprising a ramp voltage generator and a variable input source, both of which have a common reference voltage;

a comparator having one input connected to said ramp voltage generator and another input connected to said variable input source, the output of said comparator providing that a timeimpulse output signal is generated when the ramp voltage at the one input is less than the variable input signal at the other input;

a utilization device connected to the output of said comparator operable in response to Said time-impulse signal; and

a ramp characterization means for providing that the ramp signal does not quite return to said common reference voltage at the beginning of each cycle, but to a predetermined fixed voltage value, equal to a fraction of the maximum voltage value, for a time period corresponding to the time period it would normally take the ramp voltage to reach said predetermined voltage value, whereby input signals below said predetermined voltage value will not produce a time-impulse output signal.

2. A circuit as defined in claim 1, in which said ramp voltage generator includes a pulse source, a binary counter, and a digital-to-analog converter for converting a predetermined number of pulses counted by said binary counter into a ramp signal.

3. A circuit as defined in claim 2 in which said ramp characterization means comprises a plurality of logic devices each having one of its inputs connected to a respective one of a plurality of counter cells corresponding to the lowest significant bits of said binary counter.

4. A circuit as defined in claim 3, in which said ramp characterization means further comprises a flip flop device having an output connected in common to the other inputs of said logic devices, the outputs of said logic devices being connected to said digital-to-analog converter.

5. A circuit as defined in claim 4 in which the pulse width of the time-impulse signals is directly proportional with the magnitude of the input signals.

6. A circuit as defined in claim 5, further including a device for sensing the predetermined count and for resetting said counter.

7. A circuit as defined in claim 6 in which said sensing device is connected to said flip flop device.

8. A circuit as defined in claim 1, further including input conditioning and ranging circuitry at the input to said comparator for converting variable input signals to prescribed ranges.

9. A circuit as defined in claim 1, further including output circuitry for translating the comparator output signal, which includes positive and negative portions, into a signal of single polarity.