EXPANSION/COMPRESSION AND ELASTIC BUFFER COMBINATION

• US 3,825,899 A
• Filed: 08/11/1971
• Issued: 07/23/1974
• Est. Priority Date: 08/11/1971
• Status: Expired due to Term

• Current Assignee: Heinz H. Haeberle, John M. Husted
• Original Assignee: Heinz H. Haeberle, John M. Husted
• Inventors: Husted, John M., Haeberle, Heinz H.
• Primary Examiner(s): Shaw, Gareth D.
• Application Number:
  US05/170,933
• Time in Patent Office: 1,077 Days
• Field of Search: 179/15BA,15BS 340/172.5
• US Class Current: 370/324
• CPC Class Codes: H04B 7/2125 Synchronisation
• CPC Class Codes: H04B 7/2126 using a reference station
• CPC Class Codes: H04J 3/062 Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers pulse-stuffing H04J3/07; asynchronous-synchronous conversion H04L5/24; speed conversion H04L25/05; speed conversion in computers G06F5/06

Abstract

In a satellite transponder communications system operating in a time division multiple access mode, each earth station transmits data in a burst format. All bursts within a single transponder frame are synchronized to a special reference burst which contains no data communications. A single earth station sends out the reference burst as well as its normal burst, and in the case of a multitransponder and multi transponder frames, the single reference station sends out all of the reference bursts for the various transponder frames. Data to be transmitted may be received in many different forms and included within the same burst because of the modular arrangement of the earth stations. Individual terrestrial interface modules receive data in various forms, convert the data into bit form which is compatible with the TDMA system, store the converted bit stream and hold the compressed block of data until a multiplexer requests the block of data for inclusion into the earth stations transmitted burst. The arrangement of blocks of data within a burst and the timing and duration of a burst is controlled by digital words stored in a memory. Complete reordering of burst times and the arrangement of blocks of data within a burst is accomplished by changing the words stored in the memory. A comparable system on the receive side of the earth station extracts blocks of data in selected bursts for conveyance to selected terrestrial interface modules. A terrestrial interface module is provided for receiving data at a rate asynchronous with the TDMA bits rate and adding or subtracting dummy bit where necessary to provide the data out of the terrestrial interface module at a rate synchronized to the TDMA bit rate. The elastic buffer and compression/expansion buffer functions, necessary for handling asynchronous data and confining the data to assigned burst times, respectively, are combined in a single elastic-compression buffer on the transmit side and a single elastic-expansion buffer at the receive side.

Claims

1. In a time division multiple access (TDMA) communications system having a fixed frame rate determined by frame reference pulses, the improvement comprising, a. first means adapted to receive information bits at a rate which is not synchronized to said fixed frame rate;

b. means for detecting the number of information bits received during each said fixed frame;

c. means responsive to said detecting means and to said received information bits for temporarily storing the information bits received each frame;

d. means responsive to said detecting means for generating and temporarily storing a code word identifying the number of information bits received and stored in a frame; and

e. means responsive to a predetermined number of clock pulses synchronized to said frame rate and occurring each frame, for reading out from said code word storing means and said information bit storage means, a fixed number of bits, dependent upon the number of said clock pulses, said fixed number of bits always including all information bits stored during the previous frame.

2. A system as claimed in claim 1 wherein said means for generating and storing a code word comprises means responsive to said detecting means for generating said code word only in response to said detecting means detecting a number of information bits per frame different than preset number corresponding to the nominal number of information bits per frame.

3. A system as claimed in claim 2 wherein said means for reading out comprises means responsive to a first group of said clock pulses for reading out from said code storage means less than the entire code word, wherein said stored code word is read out and submultiplexed over a number of frames.

4. A system as claimed in claim 1 wherein said means for generating and storing a code word comprises means responsive to said detecting means for generating and storing a code word each frame identifying the number of information bits received and stored during said frame.

5. A system as claimed in claim 4 wherein said read out means comprises means responsive to a number of said clock pulses equal in number to the number of bits in said code word for reading out said complete code word, wherein a code word is completely read out each frame and included in said fixed number of bits.

6. A system as claimed in claim 1 wherein said detecting means comprises, a. a counter adapted to count clock pulses occurring at the information bit rate, and provide a first output pulse when said counter reaches a predetermined number, x;

b. a phase comparator responsive to said first pulses and said frame reference pulses for providing an output representing the out-of-phase condition of said first pulses and said frame reference pulses.

7. A system as claimed in claim 6 further comprising means responsive to said code generating means for causing said counter to recycle at a count corresponding to the number represented by said code word.

8. A system as claimed in claim 6 wherein said information bit storAge means comprises:

a. first and second buffer storage means, each adapted to write in information bits applied thereto when write-enabled and to read out their contents when read-enabled, and b. read-write enabling means responsive to the recycling of said counter and said predetermined number of clock pulses for alternately write-enabling said first and second buffer storage means and read-enabling said first and second storage means each recycle of said counter, one of said buffer storage means being read-enabled while the other is write-enabled.

9. A system as claimed in claim 8 further comprising:

a. receiver storage means;

b. means responsive to said code word in said fixed number of bits for gating only the information bits in said fixed number of bits into said receiver storage means; and

c. means responsive to said code word and to said frame reference pulses for reading out the information bits in said receiver storage means at a rate corresponding to the said information bit rate.